3.5.3 Additional XO Input Options
For flexibility, the EVM provides additional XO input options (use one at a time). C70 allows an external
reference to be provided at SMA connector XO (J8). C71 allows one of the onboard XO/TCXO/OCXO footprints
to be used.
By default, Y1 is populated with a 48-MHz TCXO and selected with the populated R43 and R206. R43 provides
the output clock of Y1 to the XO pin of the LMK5B33414 and R206 provides power to Y1.
Additional PCB footprints are available to install alternate components for performance evaluation of specific
oscillators. These additional footprints are Y2 (2.5 × 2.0 mm), Y3 (3.2 mm × 2.5 mm), Y4 (9.7 mm × 7.5 mm), Y5
(25 mm × 22 mm), and U4 (2.5 mm × 2 mm).
When using Y2, Y3, Y4, Y5, or U4, R43 and R206 must be removed to power down and isolate the output of
Y1. When populating Y2, R46 and R207 must be populated to power up Y2 and provide its output to the XO pin.
When populating Y3, R47 must be populated to provide Y3's output to the XO pin. When populating Y4, R48
must be populated to provide Y4's output to the XO pin. When populating Y5, R49 must be populated to provide
Y5's output to the XO pin. When populating U4, R50 must be populated to provide U4's output to the XO pin.
shows the components described above.
Take care if more than one device is installed to remove resistors to power down unused oscillators and isolate
their outputs as described above.
3.5.4 APLL Reference Options
The LMK5B33414 APLLs may accept any other APLL output as a reference instead of the XO. The BAW
on APLL3 provides a good option for a high-frequency cascaded APLL reference.
configure the APLL reference to be cascaded from another APLL.
3.6 Reference Clock Inputs
The LMK5B33414 has four DPLL reference clock input pairs (IN0_P/N, IN1_P/N, IN2_P/N, and IN3_P/N) with
configurable input priority and input selection modes. The inputs have programmable input type, termination, and
biasing options to support any clock interface type.
External LVCMOS or differential reference clock inputs can be applied to the SMA ports, labeled IN0_P/N,
IN1_P/N, IN2_P/N, and IN3_P/N. All SMA inputs are routed through 50-Ω single-ended traces. To accommodate
evaluation of different input types, the EVM default assembly supports two AC-coupled differential inputs
(IN2_P/N and IN3_P/N), one DC-coupled differential input (IN1_P/N) and one DC-coupled single-ended input
(IN0_P). When applying a single-ended signal, connect to the noninverting input (IN0_P, IN1_P, IN2_P, or
IN3_P).
3.7 Clock Outputs
The LMK5B33414 has 14 clock output pairs (OUT[0:13]_P/N).
OUT0 is configured as DC-coupled for LVCMOS evaluation purposes. OUT1, OUT2, and OUT3 have 50 Ω to
GND followed by an AC-coupling capacitor for HCSL evaluation purposes. OUT4 to OUT13 are AC-coupled to
the SMA ports for LVDS and HSDS evaluation purposes.
WARNING
DC-coupled clocks should not be directly connected to RF equipment which cannot accept DC
voltage greater than 0 V. For example, spectrum analyzers and phase noise analyzers.
3.8 Status Outputs and LEDS
Status outputs signals can be configured on the GPIO0, GPIO1, and GPIO2 pins. The status output types are
3.3-V LVCMOS or NMOS open-drain.
EVM Configuration
SNAU279 – JULY 2022
LMK5B33414EVM User's Guide
13
Copyright © 2022 Texas Instruments Incorporated
