8 Schematic
0.1
µ
F
C3
1
µ
F
C2
GND
VDD
GND
0
R9
100
R5
100
R17
VDD
GND
Y0
Y0
0
R25
100
R21
100
R33
VDD
GND
Y1
0
R11
100
R6
100
R18
VDD
GND
Y2
Y2
0
R27
100
R22
100
R34
VDD
GND
Y3
Y3
GND
GND
GND
GND
10uF
C1
5pF
C6
5pF
C10
5pF
C7
5pF
C11
L1
TP1
0.1
µ
F
C4
0.1
µ
F
C5
0
R10
0
R26
0
R12
0
R28
TP2
GND
Y1
1
2
J1
1
2
3
4
5
J4
1
2
3
4
5
J5
1
2
3
4
5
J8
1
2
3
4
5
J9
GND
VDD
Y0
Y1
Y2
Y3
Y0
Y1
Y2
Y3
100
R1
100
R3
GND
VDD
1
2
3
J3
GND
VDD
0
R4
GND
0
R2
CLKIN
1G
1
2
3
4
5
J2
CLKIN
1
1G
2
Y0
3
GND
4
Y2
5
VDD
6
Y3
7
Y1
8
LMK1C1104PW
U1
Place decoupling
caps close to
device
Figure 8-1. LMK1C1104 Schematic
Schematic
SNAU249A – DECEMBER 2019 – REVISED DECEMBER 2020
LMK1C1104 Low-Additive, Phase-Noise LVCMOS Clock Buffer Evaluation Board
5
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