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Revised - August 2014 

LMK04800 Family 

         SNAU076B       

25

 

Copyright © 2014, Texas Instruments Incorporated

 

www.ti.com

 

Single Loop 0-Delay Mode Examples 

In Single Loop 0-Delay Mode, MODE = 8, the feedback from the VCO of PLL2 to the PLL2_P/PLL2 N 
divider is broken and a fed back clock output will drive the PLL2 N divider directly.  This permits phase 
alignment between the clock output and the OSCin input (0-Delay).  As such, the PLL2_N, PLL2_R, and 
PLL2_N_CAL divide values may need to be adjusted to permit the LMK04800 to lock. 

Programming Steps 

1.

 

Program the Single Loop 0-Delay mode. 

2.

 

Enable the feedback mux.  EN_FEEDBACK_MUX = 1. 

3.

 

Select clock output for feedback with the feedback mux.  FEEDBACK_MUX = User value. 

4.

 

Program the VCO frequency of PLL2 tab to: The actual VCO frequency * PLL2_P (which is 
PLL2 PreN) / CLKout Divider. 

•

 

Entered CodeLoader 4 VCO Frequency = Actual VCO Frequency * PLL2_P / CLKout 
Divider. 

5.

 

Updated the PLL2_N_CAL register on the Bits/Pins tab to the N value when in non-0-Delay mode. 

6.

 

Press Ctrl-L to cause all registers to be programmed. 

•

 

The reason is to cause the programming of register R30 to start the VCO calibration 
routine now that the proper PLL2_N_CAL value is programmed. 

•

 

PLL2_N_CAL value is automatically updated when a new VCO frequency is entered and 
the PLL2_N value is calculated.  In this case the VCO frequency entered is wrong and the 
PLL2_N_CAL value will be incorrect. 

 
If for any reason the CLKout frequency is less than the phase detector frequency, the PLL2 R divider 
must be increased so that the phase detector is at the same or lower value than the CLKout frequency. 

Details 

The 0-Delay mode for Single Loop mode is more complicated to program than for Dual Loop mode in 
part because of the PLL2_N_CAL register.  When performing the VCO calibration the device uses 
PLL2_N_CAL for in non-0-Delay mode.  Once the VCO is calibrated the device enters 0-Delay mode.  
For more information on the PLL programming equations, refer to PLL PROGRAMMING in the 
applications section of the datasheet.  
 
In Table 7 case 1 illustrates the register programming when note using 0-Delay. 
 
Case 2 shows 0-Delay with a clock out divider of 2.  Since PLL2_P = 2, this substitution of which circuit 
is performing the divide by two results in no impact o the software.  All the values display correctly. 
 
Case 3 shows 0-Delay mode with a CLKout divider not equal to the PLL2_P value.  So the proper 
frequency to program in the VCO to lock the VCO to 2949.12 MHz will be 491.52 MHz.  This is 
calculated by Actual VCO Frequency * PLL2_P / CLKoutX_Y_DIV. 
 
Case 4 shows 0-Delay mode with CLKout divider not equal to the PLL2_P value; however the CLKout 
frequency will be less than the current phase detector frequency.  This requires PLL2_R to be increased 
from a value of 1 to 2 to reduce the PLL2 phase detector frequency from 122.88 MHz to 61.44 MHz.  
Now the adjusted VCO frequency can be programmed to allow PLL2 to lock. 

Содержание LMK04803B

Страница 1: ...LMK048xx Evaluation Board User s Guide August 2011 SNAU076B Revised August 2014 ...

Страница 2: ...2 SNAU076B LMK04800 Family Revised August 2014 Copyright 2014 Texas Instruments Incorporated www ti com Low Noise Clock Jitter Cleaner with Dual Loop PLLs Evaluation Board Operating Instructions ...

Страница 3: ...CK OUTPUTS 10 PLL LOOP FILTERS AND LOOP PARAMETERS 12 PLL 1 LOOP FILTER 12 122 88 MHz VCXO PLL 12 PLL2 LOOP FILTER 13 Integrated VCO PLL 13 EVALUATION BOARD INPUTS AND OUTPUTS 14 RECOMMENDED TEST EQUIPMENT 22 PROGRAMMING 0 DELAY MODE IN CODELOADER 23 OVERVIEW 23 DUAL LOOP 0 DELAY MODE EXAMPLES 23 Programming Steps 23 Details 23 SINGLE LOOP 0 DELAY MODE EXAMPLES 25 Programming Steps 25 Details 25 A...

Страница 4: ...ND OSCOUT1 OUTPUT 52 CLOCK OUTPUTS OSCOUT0 CLKOUT0 TO CLKOUT3 53 CLOCK OUTPUTS CLKOUT4 TO CLKOUT7 54 CLOCK OUTPUTS CLKOUT8 TO CLKOUT11 55 UWIRE HEADER LOGIC I O PORTS AND STATUS LEDS 56 USB INTERFACE 57 APPENDIX D BILL OF MATERIALS 58 APPENDIX E PCB LAYERS STACKUP 68 APPENDIX F PCB LAYOUT 69 LAYER 1 TOP 69 LAYER 2 RF GROUND PLANE INVERTED 70 LAYER 3 VCC PLANES 71 LAYER 4 GROUND PLANE INVERTED 72 L...

Страница 5: ...lease see EVM Software and Communication for more information Available LMK048xx Evaluation Boards The LMK048xx Evaluation Board supports any of the four devices offered in the LMK04800 Family All evaluation boards use the same PCB layout and bill of materials except for the corresponding LMK0480xxB device affixed to the board A commercial quality VCXO is also mounted to the board to provide a kno...

Страница 6: ...e device 2 Connect a reference clock from a signal source to the CLKin1 SMA port Use 122 88 MHz for default The reference frequency depends on the device programming 3 Please see Appendix G for quick start on interfacing the board 4 Program the device with a default mode using CodeLoader Ctrl L must be pressed at least once to load all registers Alternatively click menu Keyboard Controls Load Devi...

Страница 7: ... to enable the output under test to make measurements Table 3 Default CodeLoader Modes for LMK04808 Default CodeLoader Mode Device Mode CLKin Frequency OSCin Frequency 122 88 MHz CLKin1 122 88 MHz VCXO Dual PLL Internal VCO 122 88 MHz 122 88 MHz 122 88 MHz CLKin1 Dual Loop 0 delay 122 88 MHz VCXO Dual PLL Internal VCO 0 Delay with Internal Feedback 122 88 MHz 122 88 MHz 122 88 MHz CLKin1 122 88 MH...

Страница 8: ...ader Before proceeding be sure to follow the Quick Start section above to ensure proper connections 1 Start CodeLoader 4 Application Click Start Programs CodeLoader 4 CodeLoader 4 The CodeLoader 4 program is installed by default to the CodeLoader 4 application group 2 Select Device Click Select Device Clock Conditioners LMK04808B Once started CodeLoader 4 will load the last used device To load a n...

Страница 9: ...p isn t really needed but included to emphasize the importance of pressing Ctrl L to load the device at least once after starting CodeLoader restoring a mode or restoring a saved setup using the File menu See Appendix A CodeLoader Usage or the CodeLoader 4 instructions located at http www ti com tool codeloader for more information on Port Setup Appendix H Troubleshooting Information contains info...

Страница 10: ...settings as needed a Digital Delay value b Clock Divider value c Analog Delay select and Analog Delay value if not Bypassed d Clock Output type 4 Depending on the configured output type the clock output SMAs can be interfaced to a test instrument with a single ended 50 ohm input as follows a For LVDS i A balun like ADT2 1T is recommended for differential to single ended conversion b For LVPECL i A...

Страница 11: ...m 5 The phase noise may be measured with a spectrum analyzer or signal source analyzer See Appendix B Typical Phase Noise Performance Plots for phase noise plots of the clock outputs Texas Instruments Incorporated s Clock Design Tool can be used to calculate divider values to achieve desired clock output frequencies See http www ti com tool clockdesigntool ...

Страница 12: ...row loop bandwidth 100 Hz while the loop filter of PLL2 has been configured for a wide loop bandwidth 100 kHz The specific loop bandwidth values depend on the phase noise performance of the oscillator mounted on the board The following tables contain the parameters for PLL1 and PLL2 for each oscillator option Texas Instruments Incorporated s Clock Design Tool can be used to optimize PLL phase nois...

Страница 13: ...2_A2 3 9 nF C3 internal 0 nF C4 internal 0 nF R2_A2 0 62 kΩ R3 internal 0 2 kΩ R4 internal 0 2 kΩ Charge Pump Current Kφ 3 2 mA Phase Detector Frequency 122 88 MHz Frequency 1966 08 2211 84 2457 6 2949 12 MHz Kvco 17 9 16 5 18 8 32 3 MHz V N 16 18 20 24 Phase Margin 75 75 75 76 degrees Loop Bandwidth 355 320 321 424 kHz Note PLL Loop Bandwidth is a function of Kφ Kvco N as well as loop components ...

Страница 14: ...CLKout7 CLKout7 CLKout9 CLKout9 CLKout11 CLKout11 Analog Output Clock outputs with programmable output buffers The output terminations by default on the evaluation board are shown below and the output type selected by default in CodeLoader is indicated by an asterisk Clock output pair Default Board Termination CLKout0 LVPECL CLKout1 LVPECL CLKout2 LVPECL CLKout3 LVPECL CLKout4 LVDS LVCMOS CLKout5 ...

Страница 15: ...e Both OSCout pairs are AC coupled to allow safe testing with RF test equipment The OSCout1 output is source terminated using 240 ohm resistors If OSCout0 is programmed as LVCMOS each output can be independently configured normal inverted inverted and off tri state Vcc Power Input Main power supply input for the evaluation board A 3 9 V DC power source applied to this SMA will by default source th...

Страница 16: ...opulated VccVCO Aux Power Input Optional Vcc input to power the VCO circuit if separated voltage rails are needed The VccVCO Aux input can power these circuits directly or supply the on board LDO regulators 0 Ω resistor options provide flexibility to route power Populated VccVCXO Aux Power Input Optional Vcc input to power the VCXO circuit if separated voltage rails are needed The VccVCXO Aux inpu...

Страница 17: ...ed in CodeLoader The clock input selection mode can be programmed on the Bits Pins tab via the CLKin_Select_MODE control Refer to the LMK04800 Family Datasheet section Input Clock Switching for more information AC coupled Input Clock Swing Levels Input Mode Min Max Units Differential Bipolar or CMOS 0 5 3 1 Vpp Single Ended 0 25 2 4 Vpp External Feedback Input FBCLKin for 0 Delay CLKin1 is shared ...

Страница 18: ... AC coupled If operated in single ended mode the unused input must be connected to GND with 0 1 uF Refer to the LMK04800 Family Datasheet section Electrical Characteristics for PLL2 Reference Input OSCin specifications Test point VTUNE1_TP Not populated Vtune1 Analog Output Tuning voltage output from the loop filter for PLL1 If a VCXO add on board is used this tuning voltage can be connected to th...

Страница 19: ...efore a high frequency internal signal e g PLL divider output signal is selected by LD_MUX it is suggested to first remove the 270 ohm resistor to prevent the LED from loading the output Test point Holdover_TP Not populated Status_Hold CMOS Output Programmable status output pin By default set to the output holdover mode status signal In the default CodeLoader mode LED D8 will illuminate red when h...

Страница 20: ...ck Switching Pin Select Mode When CLKin_SELECT_MODE is 3 the Status_CLKinX pins select which clock input is active as follows Status_CLKin1 Status_CLKin0 Active Clock 0 0 CLKin0 0 1 CLKin1 1 0 Reserved 1 1 Holdover Input Clock Switching Auto with Pin Select When CLKin_SELECT_MODE is 6 the active clock is selected using the Status_CLKinX pins upon an input clock switch event as follows Status_CLKin...

Страница 21: ...deLoader mode SYNC will asserted when the SYNC pin is low and the outputs to be synchronized will be held in a logic low state When SYNC is unasserted the clock outputs to be synchronized are activated and will be initially phase aligned with each other except for outputs programmed with different digital delay values A SYNC event can also be programmed by toggling the SYNC_POL_INV bit in the Bits...

Страница 22: ...erior for phase noise measurements At frequencies less than 100 MHz the local oscillator noise of the E4445A is too high and measurements will reflect the E4445A s internal local oscillator performance not the device under test Oscilloscope To measure the output clocks for AC performance such as rise time or fall time propagation delay or skew it is suggested to use a real time oscilloscope with a...

Страница 23: ...rkaround and some example cases Dual Loop 0 Delay Mode Examples In Dual Loop 0 Delay Modes MODE 2 or MODE 5 the feedback from the VCXO of PLL1 to the PLL1 N divider is broken and a clock output will drive the PLL1 N divider This permits phase alignment between the clock output and the clock input 0 Delay As such the PLL1_N and PLL1_R divide values may need to be adjusted to permit the LMK04800 to ...

Страница 24: ...ation 122 88 MHz CLKin 122 88 MHz VCXO of the LMK04808 has the following register programming Case 1 Default Mode No 0 Delay Case2 Default 0 Delay Mode CLKout8 122 88 MHz Case 3 Default 0 Delay Mode Updated CLKout8 245 76 MHz Case 4 Default 0 Delay Mode Updated CLKout8 61 44 MHz Actual PLL1 VCXO Frequency 122 88 122 88 122 88 122 88 Reported PLL1 VCXO Frequency 122 88 122 88 61 44 245 76 PLL1 N 12...

Страница 25: ...the PLL2_N_CAL value will be incorrect If for any reason the CLKout frequency is less than the phase detector frequency the PLL2 R divider must be increased so that the phase detector is at the same or lower value than the CLKout frequency Details The 0 Delay mode for Single Loop mode is more complicated to program than for Dual Loop mode in part because of the PLL2_N_CAL register When performing ...

Страница 26: ... Table 7 Single PLL 0 Delay Operation Examples Case 1 Default Mode No 0 Delay Case 2 Default 0 Delay Mode CLKout8 1474 56 MHz Case 3 Default 0 Delay Mode Updated CLKout8 245 76 MHz Case 4 Default 0 Delay Mode Updated CLKout8 61 44 MHz Actual PLL2 VCO Frequency 2949 12 MHz 2949 12 MHz 2949 12 MHz 2949 12 MHz Reported PLL2 VCO Frequency 2949 12 MHz 2949 12 MHz 491 52 MHz 122 88 MHz PLL2_R 1 1 1 2 PL...

Страница 27: ...with LPT or USB2ANY uWire interface available from www ti com Port Setup Tab Figure 8 Port Setup tab On the Port Setup tab the user may select the type of communication port LPT or USB that will be used to program the device on the evaluation board The Pin Configuration field is hardware dependent and normally does not need to be changed by the user Figure 8 shows the default settings ...

Страница 28: ...om either VCO or OSCin via OSC Mux1 and OSC Mux2 Channel Powerdown affects digital and analog delay clock divider and buffer blocks Digital Delay value and Half Step Clock Divide value Analog Delay value and Delay bypass enable per output Clock Output format per output This tab also allows the user to select the VCO Divider value 2 to 8 Note that the total PLL2 N divider value is the product of th...

Страница 29: ...4 allow one to step through the possible values Left click to increase the component value and right click to decrease the value These values can also be changed in the Bits Pins tab The Reference Oscillator value field may be changed in either the Clock Outputs tab or the PLL2 tab The PLL2 Reference frequency should match the frequency of the onboard VCXO or Crystal i e VCO frequency in the PLL1 ...

Страница 30: ...ble 8 Table 8 Registers Controls and Descriptions in PLL1 tab Control Name Register Name Description Reference Oscillator Frequency MHz n a CLKin frequency of the selected reference clock Phase Detector Frequency MHz n a PLL1 Phase Detector Frequency PDF This value is calculated as PLL1 PDF CLKin Frequency PLL1_R CLKinX_PreR_DIV where CLKinX_PreR_DIV is the predivider value of the selected input c...

Страница 31: ...ence Frequency When operating in Dual PLL mode without 0 delay feedback the VCO frequency value on the PLL1 tab must match the Reference Oscillator OSCin frequency value on the PLL2 tab otherwise the one or both PLLs may be out of lock Updating the Reference Oscillator frequency on the PLL2 tab will automatically update the value of OSCin_FREQ on the Bits Pins tab However when operating in Dual PL...

Страница 32: ...External VCXO or Crystal Phase Detector Frequency MHz n s PLL2 Phase Detector Frequency PDF This value is calculated as PLL2 PDF OSCin Frequency 2EN_PLL2_REF_2X PLL2_R VCO Frequency MHz n a Internal VCO Frequency should be within the allowable range of the LMK048xxB device This value is calculated as VCO Frequency PLL2 PDF PLL2_N PLL2_P VCO divider value Doubler EN_PLL2_REF_2X PLL2 Doubler 0 Bypas...

Страница 33: ...anges made on this tab will be reflected in the Clock Outputs tab The VCO Frequency should conform to the specified internal VCO frequency range for the LMK048xxB device per Table 2 Bits Pins Tab Figure 13 Bits Pins tab The Bits Pins tab allows the user to program bits directly many of which are not available on other tabs Brief descriptions for the controls on this tab are provided in Table 10 to...

Страница 34: ...VCO divider to drive the clock distribution path The VCO divider is only valid if MODE is selecting the Internal VCO uWire_LOCK When checked no other uWire programming will have effect Must be unchecked to enable uWire programming of registers R0 to R30 CLKin CLKin_Select_MODE Selects operational mode for how the device selects the reference clock for PLL1 EN_CLKin1 Enables CLKin1 as a usable refe...

Страница 35: ...tputs where X even numbered output and Y odd numbered output SYNC_QUAL Sets the SYNC to qualify mode for dynamic digital delay EN_SYNC Must be set when using SYNC but may be cleared after the SYNC event When using dynamic digital delay SYNC_QUAL 1 EN_SYNC must always be set Changing this value from 0 to 1 can cause a SYNC event so clocks which should not be SYNCed when setting this bit should have...

Страница 36: ...on the clock switch event NOTE EN_VTUNE_RAIL_DET must be enabled for this to be valid DAC_HIGH_TRIP Value from VCC 3 3V in 50mV steps at which clock switch event is generated If Holdover mode is enabled it will be engaged upon the clock switch event NOTE EN_VTUNE_RAIL_DET must be enabled for this to be valid PLL1 PLL1_WND_SIZE If the phase error between the PLL1 reference and feedback clocks is le...

Страница 37: ...d by PLL2_WND_SIZE for this many cycles before PLL2 digital lock detect is asserted EN_PLL2_REF_2X Enables the doubler block to doubles the reference frequency into the PLL2 R counter This can allow for frequency of 2 3 2 5 etc of OSCin to be used at the phase detector of PLL2 PLL2_N_CAL The PLL2_N_CAL register contains the N value used for the VCO calibration routine Except during 0 delay modes t...

Страница 38: ...gisters Tab The Registers tab shows the value of each register This is convenient for programming the device to the desired settings then exporting to a text file the register values in hexadecimal for use in your own application By clicking in the bit field it is possible to manually change the value of registers by typing 1 and 0 ...

Страница 39: ...lock phase noise measurements with the Crystek 122 88 MHz VCXO Table 11 LMK048xxB Test Conditions Parameter Value PLL1 Reference clock input CLKin0 single ended input CLKin0 AC coupled to GND PLL1 Reference Clock frequency 122 88 MHz PLL1 Phase detector frequency 122 88 MHz PLL1 Charge Pump Gain 100 uA VCXO frequency 122 88 MHz PLL2 phase detector frequency 122 88 MHz PLL2 Charge Pump Gain 3200 uA...

Страница 40: ...MHz 22 7 Clock Output Measurement Technique The same technique was used to measure phase noise for all three output types available on the programmable OSCout and CLKout buffers This was achieved by terminating one side of the LVPECL LVDS or LVCMOS output with a 50 ohm load and measuring the other side single ended using an Agilent E5052B Source Signal Analyzer Buffered OSCout Phase Noise Both OSC...

Страница 41: ...e Noise and RMS Jitter fs Offset 1474 56 MHz LVDS 1474 56 MHz LVPECL 491 52 MHz LVDS 491 52 MHz LVPECL 100 Hz 88 2 87 8 97 7 99 7 1 kHz 109 8 108 9 118 9 119 3 10 kHz 118 0 117 4 127 3 127 4 100 kHz 119 8 119 7 129 1 129 4 800 kHz 130 9 130 8 140 1 140 3 1 MHz 132 7 132 6 141 7 142 1 10 MHz 148 2 149 2 152 7 154 9 20 MHz 148 9 150 1 153 2 155 3 RMS Jitter fs 10 kHz to 20 MHz 99 3 99 4 109 1 103 3 ...

Страница 42: ...Offset 245 76 LVDS 245 76 LVCMOS 245 76 LVPECL 122 88 LVDS 122 88 LVCMOS 122 88 LVPECL 100 Hz 103 7 104 4 106 1 108 4 110 4 108 5 1 kHz 123 7 125 9 125 7 128 7 129 7 130 9 10 kHz 133 8 133 5 134 0 139 3 139 8 140 0 100 kHz 135 5 135 4 135 8 141 7 141 4 141 8 800 kHz 146 4 146 3 146 7 151 7 152 1 152 4 1 MHz 147 9 148 0 148 3 152 9 153 4 153 8 10 MHz 156 5 157 5 158 3 158 7 160 5 161 0 20 MHz 156 9...

Страница 43: ...0 LVPECL OSCout1 LVPECL OSCin thru CLKout 100 Hz 110 2 111 1 109 4 1 kHz 137 2 136 1 138 6 10 kHz 148 0 148 0 146 7 100 kHz 157 8 156 0 155 3 800 kHz 159 1 159 4 156 4 1 MHz 157 0 157 5 156 3 10 MHz 158 8 159 2 156 7 20 MHz 159 2 159 5 156 7 RMS Jitter fs 10 kHz to 20 MHz 94 1 91 0 123 7 RMS Jitter fs 100 Hz to 20 MHz 103 2 99 6 131 3 Title Title 122 88 MHz LVCMOS OSCin through CLKout 122 88 MHz O...

Страница 44: ...1 2 129 5 129 5 800 kHz 133 8 133 7 141 9 141 9 1 MHz 135 8 135 7 143 4 143 8 10 MHz 150 2 150 4 153 1 155 7 20 MHz 150 8 151 0 153 8 155 7 RMS Jitter fs 10 kHz to 20 MHz 92 9 93 4 97 5 94 5 RMS Jitter fs 100 Hz to 20 MHz 104 0 105 3 109 0 105 4 For the LMK04806B the internal VCO frequency is 2457 60 MHz The divide by 10 CLKout frequency is 245 76 MHz and the divide by 20 CLKout frequency is 122 8...

Страница 45: ... LVPECL 100 Hz 105 8 104 5 106 5 108 6 113 0 111 4 1 kHz 124 7 124 9 125 4 130 2 132 1 131 0 10 kHz 134 8 134 4 134 9 140 7 140 7 141 0 100 kHz 135 5 135 4 135 8 141 7 141 7 141 9 800 kHz 147 8 147 7 148 0 152 6 153 5 154 1 1 MHz 149 6 149 4 149 7 153 3 155 2 155 5 10 MHz 156 1 158 1 158 4 158 4 161 5 161 1 20 MHz 156 3 158 2 158 9 159 5 161 6 161 3 RMS Jitter fs 10 kHz to 20 MHz 106 9 101 5 96 4 ...

Страница 46: ...0 LVPECL OSCout1 LVPECL OSCin thru CLKout 100 Hz 110 3 112 1 110 0 1 kHz 136 9 137 9 138 9 10 kHz 151 1 150 1 150 0 100 kHz 154 3 156 8 154 6 800 kHz 158 9 158 9 156 6 1 MHz 159 2 159 1 156 6 10 MHz 159 4 160 0 156 8 20 MHz 157 6 159 9 156 9 RMS Jitter fs 10 kHz to 20 MHz 138 4 89 7 120 0 RMS Jitter fs 100 Hz to 20 MHz 143 7 97 3 126 2 Title Title 122 88 MHz LVCMOS OSCin through CLKout 122 88 MHz ...

Страница 47: ... 127 8 128 3 800 kHz 134 9 134 5 140 3 140 8 1 MHz 136 8 136 3 142 0 142 7 10 MHz 150 3 150 6 152 0 154 2 20 MHz 150 4 151 1 152 6 154 6 RMS Jitter fs 10 kHz to 20 MHz 103 8 107 4 116 0 108 1 RMS Jitter fs 100 Hz to 20 MHz 116 1 116 2 127 4 116 8 For the LMK04803B the internal VCO frequency is 1966 08 MHz The divide by 8 CLKout frequency is 245 76 MHz and the divide by 16 CLKout frequency is 122 8...

Страница 48: ...LVPECL 100 Hz 104 8 104 2 108 4 112 1 111 5 112 7 1 kHz 124 8 123 5 125 0 130 5 130 2 130 6 10 kHz 133 7 134 0 133 6 140 1 139 8 140 1 100 kHz 134 4 134 4 134 6 140 6 140 4 140 7 800 kHz 146 7 146 7 147 1 152 5 152 4 152 7 1 MHz 148 5 148 5 148 7 153 4 154 0 154 0 10 MHz 156 2 157 2 158 0 158 4 160 1 160 5 20 MHz 156 6 157 5 158 2 158 7 160 4 161 1 RMS Jitter fs 10 kHz to 20 MHz 115 1 113 1 107 9 ...

Страница 49: ...t1 LVPECL OSCin thru CLKout 100 Hz 114 0 113 1 113 3 1 kHz 136 6 137 2 138 4 10 kHz 147 6 146 6 148 5 100 kHz 156 3 156 2 154 0 800 kHz 159 4 159 2 156 6 1 MHz 159 0 159 3 156 7 10 MHz 157 2 158 7 156 9 20 MHz 158 1 159 4 157 0 RMS Jitter fs 10 kHz to 20 MHz 107 1 92 4 119 1 RMS Jitter fs 100 Hz to 20 MHz 111 6 98 1 123 3 Phase Noise dBc Hz Frequency Offset Hz 122 88 MHz LVCMOS OSCin through CLKou...

Страница 50: ...50 SNAU076B LMK04800 Family Revised August 2014 Copyright 2014 Texas Instruments Incorporated www ti com Appendix C Schematics Power Supplies ...

Страница 51: ...36 DNP 0 1µF C27 DNP C2_B2 DNP 100pF C1_B2 470 R2_B2 0 R55 0 12uF C2pB2 0 R72 DNP 0 68µF C2_A1 3 9k Rb2_B1 10µF Cb2pB1 0 33µF Cb1_B1 DNP Cb2_B1 DNP Crystal Loop Filter Y301 DNP DNP 0 R69 DNP 2pF C34 2200pF C32 2pF C28 2200pF C29 PLL2 Loop Filters PLL1 Loop Filters OSCin Tuneable Crystal 4 7k R62 1000pF C304 10k R307 VCXO Loop Filter Y300 DNP DNP VTUNE2_TP 0 R306 DNP 0 R308 DNP 0 R73 Crystal mode L...

Страница 52: ...52 SNAU076B LMK04800 Family Revised August 2014 Copyright 2014 Texas Instruments Incorporated www ti com Reference Inputs CLKin0 CLKin1 External VCXO OSCin VCO Circuits and OSCout1 Output ...

Страница 53: ...0 1µF C54 0 1µF C58 CLKout3 62 R128 DNP 120 R119 DNP 82 R120 DNP 82 R140 DNP CLKout2_N CLKout2_P CLKout2 VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane 62 R109 DNP 62 R132 DNP 62 R131 DNP 0 1µF C57 120 R139 DNP CLKout2_1_P CLKout2_1_N Notes 1 Designators greater than and equal to 300 are placed on bottom of PCB 62 R105 DNP 120 R100 DNP 82 R101 DNP 120 R11...

Страница 54: ...P 0 1µF C59 0 1µF C63 CLKout4_N CLKout4_P CLKout4 62 R171 DNP 120 R167 DNP 82 R168 DNP 120 R180 DNP 82 R181 DNP 0 1µF C66 0 1µF C70 CLKout7 62 R172 DNP 120 R165 DNP 82 R166 DNP 82 R184 DNP 0 1µF C65 CLKout6_N CLKout6_P CLKout6 VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane 62 R153 DNP 62 R176 DNP 62 R175 DNP 0 1µF C69 120 R183 DNP 62 R149 DNP 120 R145 DNP...

Страница 55: ... DNP 120 R223 DNP 82 R224 DNP 0 1µF C77 0 1µF C81 62 R193 DNP 120 R185 DNP 82 R186 DNP 120 R202 DNP 82 R203 DNP 0 1µF C71 0 1µF C75 CLKout8_N CLKout8_P CLKout8 CLKout10 CLKout10_N CLKout10_P 62 R216 DNP 120 R210 DNP 82 R211 DNP 120 R226 DNP 82 R227 DNP 0 1µF C78 0 1µF C82 CLKout11 62 R194 DNP 120 R188 DNP 82 R189 DNP 82 R205 DNP 0 1µF C72 CLKout9 VccCLKoutPlane VccCLKoutPlane VccCLKoutPlane VccCLK...

Страница 56: ...56 SNAU076B LMK04800 Family Revised August 2014 Copyright 2014 Texas Instruments Incorporated www ti com uWire Header Logic I O Ports and Status LEDs ...

Страница 57: ...Revised August 2014 LMK04800 Family SNAU076B 57 Copyright 2014 Texas Instruments Incorporated www ti com USB Interface ...

Страница 58: ...aluation Boards Item Designator Description Manufacturer PartNumber Quantity 1 C1 C5 C13 C20 C22 C25 C300 R3 R11 R12 R19 R21 R22 R29 R30 R37 R46 R55 R73 R74 R82 R84 R229 R304 R327 R329 R331 R333 R337 R340 R341 R346 R347 R349 R353 R354 R358 R361 R364 R365 R368 R371 R373 R374 R375 R400 R402 FB 120 ohm 500 mA 0603 RES 0 ohm 5 0 1W 0603 Vishay Dale Vishey Dale CRCW06030000Z0EA 47 ...

Страница 59: ...51J5GACTU 1 5 C2 C12 C41 C302 C330 C346 CAP CERM 0 1uF 16V 10 X7R 0603 Kemet C0603C104K4RACTU 6 6 C2pB2 CAP CERM 0 12uF 50V 10 X7R 0805 Kemet C0805C124K5RACTU 1 7 C2_A1 CAP CERM 0 68µF 10V 10 X5R 0603 Kemet C0603C684K8PAC 1 8 C2_A2 CAP CERM 3900pF 50V 10 X7R 0603 MuRata GRM188R71H392KA01D 1 9 C4 C69 C314 C322 C326 C367 C400 C401 C402 C409 C412 C414 CAP CERM 0 1uF 25V 10 X7R 0603 CAP CERM 0 1µF 25V...

Страница 60: ...8 C315 C323 CAP CERM 0 01uF 100V 10 X7R 0603 Kemet C0603C103K1RACTU 2 19 C340 CAP CERM 4 7uF 10V 10 X5R 0603 Kemet C0603C475K8PACTU 1 20 C350 C351 C359 C360 CAP CERM 0 47uF 16V 10 X7R 0603 Kemet C0603C474K4RACTU 4 21 C368 CAP CERM 100pF 50V 5 C0G NP0 0603 Kemet C0603C101J5GACTU 1 22 C403 CAP CERM 10uF 6 3V 10 X5R 0805 Kemet C0805C106K9PAC 1 23 C404 CAP TANT 1uF 20V 10 8 4 ohm 3216 18 SMD Vishay Sp...

Страница 61: ... 2MM 565NM RED CLR SMD Lumex Opto Components Inc SML LX2832IC 3 33 D5 LED 2 8X3 2MM 565NM GRN CLR SMD Lumex Opto Components Inc SML LX2832GC 1 34 J1 CONN TERM BLK PCB 5 08MM 2POS OR Weidmuller 1594540000 1 35 R2 R13 R36 R47 R59 R70 R332 RES 0 ohm 5 0 125W 0805 Vishay Dale CRCW08050000Z0EA 7 36 R2_A1 RES 39k ohm 5 0 1W 0603 Vishay Dale CRCW060339K0JNEA 1 37 R2_A2 RES 620 ohm 5 0 1W 0603 Vishay Dale...

Страница 62: ...hay Dale CRCW060333R0JNEA 2 48 R307 RES 10k ohm 5 0 1W 0603 Vishay Dale CRCW060310K0JNEA 1 49 R313 R316 R319 R320 R322 R325 RES 27k ohm 5 0 1W 0603 Vishay Dale CRCW060327K0JNEA 6 50 R344 RES 392 ohm 1 0 1W 0603 Vishay Dale CRCW0603392RFKEA 1 51 R345 R348 R355 R359 R362 R366 R372 FB 120 ohm 500 mA 0603 Murata BLM18AG121SN1D 7 52 R350 R369 RES 51k ohm 5 0 1W 0603 Vishay Dale CRCW060351K0JNEA 2 53 R3...

Страница 63: ...2 0701 201 1 66 VccVCO Aux VccVCXO Aux Connector SMA Jack Vertical Gold SMD Emerson Network Power Connectivity 142 0711 201 2 Unpopulated Components 67 B1 B2 B3 ADT2 1T Balun MiniCircuits ADT2 1T 0 68 C2pA1 CAP CERM 2 7uF 10V 10 X5R 0805 Kemet C0805C275K8PACTU 0 69 C2pA2 C3_AB1 C15 C17 C42 C43 C306 C307 C308 C309 CAP CERM 100pF 50V 5 C0G NP0 0603 Kemet C0603C101J5GACTU 0 70 C2_B2 CAP CERM 6800pF 1...

Страница 64: ... 0 78 CLKin0_SEL CLKin1_SEL Status_Hold Status_LD SYNC Connector SMA Jack Vertical Gold SMD Emerson Network Power Connectivity 142 0711 201 0 79 CLKout1 CLKout1 CLKout3 CLKout3 CLKout5 CLKout5 CLKout7 CLKout7 CLKout9 CLKout9 CLKout11 CLKout11 FBCLKin CLKin1 OSCin OSCin Vtune1 Connector SMT End launch SMA 50 Ohm Emerson Network Power 142 0701 851 0 80 D300 Diode Zener 3 3V 150mW SOD 523F Comchip Te...

Страница 65: ... R300 R301 R305 R306 R308 R335 R339 R352 R363 R367 R370 RES 0 ohm 5 0 1W 0603 Vishay Dale CRCW06030000Z0EA 0 85 R5 R8 R14 R25 R33 R34 R41 R48 R64 R68 R90 R96 R99 R114 R121 R135 R141 R157 R163 R179 R187 R204 R209 R225 R376 RES 51 ohm 5 0 1W 0603 Vishay Dale CRCW060351R0JNEA 0 86 R6 R7 R15 R17 R31 R32 R39 R40 R49 R50 R79 R314 RES 270 ohm 5 0 1W 0603 Vishay Dale CRCW0603270RJNEA 0 ...

Страница 66: ...161 R165 R167 R180 R183 R185 R188 R201 R202 R207 R210 R223 R226 RES 120 ohm 5 0 1W 0603 Vishay Dale CRCW0603120RJNEA 0 88 R28 R42 R65 RES 100 ohm 5 0 1W 0603 Vishay Dale CRCW0603100RJNEA 0 89 R35 R44 R89 R95 R98 R101 R116 R118 R120 R123 R137 R140 R144 R146 R160 R162 R166 R168 R181 R184 R186 R189 R203 R205 R208 R211 R224 R227 RES 82 ohm 5 0 1W 0603 Vishay Dale CRCW060382R0JNEA 0 ...

Страница 67: ... R191 R192 R199 R200 RES 240 ohm 5 0 1W 0603 Vishay Dale CRCW0603240RJNEA 0 94 R302 R303 R310 R311 R401 RES 10k ohm 5 0 1W 0603 Vishay Dale CRCW060310K0JNEA 0 95 R309 Rb2_VCO x x xxxW DNP_RES 0 96 R323 RES 2 2k ohm 5 0 1W 0603 Vishay Dale CRCW06032K20JNEA 0 97 R326 R328 R330 FB 1000 ohm 600 mA 0603 Murata BLM18HE102SN1D 0 98 R334 RES 0 ohm 5 0 125W 0805 Vishay Dale CRCW08050000Z0EA 0 99 R360 RES 5...

Страница 68: ...6 mils RF Ground plane 1 oz FR4 4 mils Power plane 1 1 oz FR4 12 6 mils Ground plane 1 oz FR4 8 mils Power Plane 2 1 oz FR4 12 mils Bottom Layer copper clad for thermal relief 2 oz RO4003 Er 3 3 16 mil Top Layer LMK048xxENG GTL RF Ground plane LMK048xxENG G1 FR4 Er 4 8 4 mil Power plane 1 LMK048xxENG G2 FR4 12 6 mil Ground plane LMK048xxENG GP1 FR4 12 mil Bottom Layer LMK048xxENG GBL 62 2 mil thic...

Страница 69: ...Revised August 2014 LMK04800 Family SNAU076B 69 Copyright 2014 Texas Instruments Incorporated www ti com Appendix F PCB Layout Layer 1 Top ...

Страница 70: ...70 SNAU076B LMK04800 Family Revised August 2014 Copyright 2014 Texas Instruments Incorporated www ti com Layer 2 RF Ground Plane Inverted ...

Страница 71: ...Revised August 2014 LMK04800 Family SNAU076B 71 Copyright 2014 Texas Instruments Incorporated www ti com Layer 3 Vcc Planes ...

Страница 72: ...72 SNAU076B LMK04800 Family Revised August 2014 Copyright 2014 Texas Instruments Incorporated www ti com Layer 4 Ground Plane Inverted ...

Страница 73: ...Revised August 2014 LMK04800 Family SNAU076B 73 Copyright 2014 Texas Instruments Incorporated www ti com Layer 5 Vcc Planes 2 ...

Страница 74: ...74 SNAU076B LMK04800 Family Revised August 2014 Copyright 2014 Texas Instruments Incorporated www ti com Layer 6 Bottom ...

Страница 75: ...Revised August 2014 LMK04800 Family SNAU076B 75 Copyright 2014 Texas Instruments Incorporated www ti com Layers 1 and 6 Top and Bottom Composite ...

Страница 76: ...the software used to communicate with the EVM Please download the latest version from TI com http www ti com tool codeloader This EVM can be controlled through the uWire interface on board There are two options in communicating with the uWire interface from the computer OPTION 1 Open Codeloader exe Click Select Device Click Port Setup tab Click LPT in Communication Mode OPTION 2 ...

Страница 77: ... F1 G1 H1 SYNC pin 7 LMK02000 A0 C1 E5 F1 G1 H1 SYNC pin 7 LMK0480x A0 B2 C3 E5 F0 G0 H1 Status_CLKin1 pin 3 LMK04816 4906 A0 B2 C3 E5 F0 G0 H1 Status_CLKin1 pin 3 LMK01801 A0 B4 C5 E2 F0 G0 H1 Test pin 3 SYNC0 pin 10 LMK0482x prelease A0 B5 C3 D2 E4 F0 G0 H1 CLKin1_SEL pin 6 Reset pin 10 LMX2531 A0 E5 F2 G1 H2 Trigger pin 1 LMX2485 7 A0 C1 E5 F2 G1 H0 ENOSC pin 7 CE pin 10 LMK03200 A0 E5 F0 G0 H1...

Страница 78: ...f not examine physical OSCin input Naturally the output frequency of the above two items PLL 1 R Divider 2 and PLL 1 N Divider 2 on LD pin should be the same frequency 5 Program LD_MUX PLL1_DLD 6 Confirm the LD pin output is high i If high then PLL1 is locked continue to PLL2 operation locking 7 If LD pin output is low but the frequencies are the same it is possible that excessive leakage on Vtune...

Страница 79: ...R programming ii If not examine physical OSCin input 3 Program LD_MUX PLL2_N 2 4 Confirm that LD pin output is half the expected phase detector frequency of PLL2 i If not confirm OSCin_FREQ is programmed to OSCin frequency ii If not examine PLL2_N programming Naturally the output frequency of the above two items should be the same frequency 5 Program LD_MUX PLL2 DLD 6 Confirm the LD pin output is ...

Страница 80: ...ring the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warranted for the remainder of the original warranty period Replaced EVMs shall be warranted for a new full ninety 90 day warranty period 3 ...

Страница 81: ... by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la rég...

Страница 82: ... connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even with the inputs and outputs kept within the specified allowable ranges some circuit components may have elevated case temperatures These components include but are not limited to linear regulators switching transistors pass transistors cu...

Страница 83: ...F REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED 8 2 Specific Limitations IN NO EVENT SHALL T...

Страница 84: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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