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Access Methods

1.2

Register Programming via SPI

Alternatively, when MODE_Sel is pulled high with 1 k

Ω

-resistor, the SPI interface is used for device

configuration. Pins associated with the SPI interface are:

* MOSI: Master Output, Slave input (pin#4)

* MISO: Master Input, Slave Output (pin#15)

* SS_N: Slave Select active low (pin#2)

* SPI_SCK: Serial clock output from master (pin#3)

The maximum operating speed supported on the SPI bus is 20 MHz.

1.3

Register Types

The LMH0318 register set is divided into four groups:

•

Global Registers- These registers are divided into share and channel registers. Share register define
LMH0318 ID, revision, enabling shared registers. Channels registers are feature specific such as
interrupt status or interrupt mask

•

Receiver Registers- These registers are associated with input stage of the device - equalizer boost
setting, signal detect levels and input mux selection.

•

Clock Data Recovery (CDR) Registers- These registers control CDR state machine, Eye Opening
Monitor (EOM), and configuration.

•

Transmitter Registers- These registers configure output multiplexers and output parameters for OUT0
and OUT1.

3

SNLU183 – September 2015

LMH0318 Programming Guide

Submit Documentation Feedback

Copyright © 2015, Texas Instruments Incorporated

Содержание LMH0318

Страница 1: ... local Texas Instruments field sales representative Contents 1 Access Methods 2 1 1 Register Programming via SMBus and SPI Interface 2 1 2 Register Programming via SPI 3 1 3 Register Types 3 2 Initialization Set Up 4 3 Register Command Syntax 5 4 Device Configuration 6 4 1 Common Device Configuration 6 4 2 Common Register Commands 7 5 Register Tables 19 5 1 Global Registers 19 5 2 Receiver Registe...

Страница 2: ... on the SMBus is 400 kHz There are 16 unique SMBus addresses that can be assigned to each device by placing external Resistor straps on the ADDR0 and ADDR1 pins pin 2 and 15 1 1 1 SMBus Slave Address ADDR0 ADDR1 ADDR0 ADDR1 7 bit SMBus Address 1 8 bit SMBus Write Address Binary Binary 1 kΩ to GND 1 kΩ to GND 00 00 0D 1A 1 kΩ to GND 20 kΩ to GND 00 01 0E 1C 1 kΩ to GND Float 00 10 0F 1E 1 kΩ to GND...

Страница 3: ...ters These registers are divided into share and channel registers Share register define LMH0318 ID revision enabling shared registers Channels registers are feature specific such as interrupt status or interrupt mask Receiver Registers These registers are associated with input stage of the device equalizer boost setting signal detect levels and input mux selection Clock Data Recovery CDR Registers...

Страница 4: ...hannel Registers 0xFF 0x04 Enable Full Temperature Range 0x16 0x25 0x3E 0x00 Initialize CDR State Machine Control 0x55 0x02 0x6A 0x00 Restore media CTLE Setting 0x03 xx Reset CDR 0x0A 0x5C Release Reset 0x0A 0x50 See LMH0318 Register Initialization for detailed register programming 4 LMH0318 Programming Guide SNLU183 September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Inc...

Страница 5: ... 01 0x80 7 1 are not modified since mask 0x01 RAR Register Register Register Mask Comments Address Content RAR Read Only Command Register Address Specifies the register address in hex format Register Content Specifies the register content that is being read Register Mask Defines the mask for register content For example 1 in a mask defines bits being read Characters following are text comments Exa...

Страница 6: ...sters RAW 16 25 FF Enable Full Temperature Range RAW 3E 00 80 Initialize CDR State Machine Control RAW 55 02 02 RAW 6A 00 FF RAW 03 XX FF Use the desired CTLE settings See CTLE Test Mode to determine the CTLE setting RAW 0A 0C 0C Reset CDR RAW 0A 00 0C Release CDR reset In default mode the LMH0318 automatically locks to different SMPTE and ST 2082 1 data rates RAR 1 1 1 Read LOS of IN0 Assuming si...

Страница 7: ...nctions CDR State Machine Reset and Register Reset 4 2 2 1 LMH0318 CDR State Machine Reset This operation should be done after changing any of the channel registers RAW FF 04 07 Select Channel Registers RAW 0A 0C 0C Reset for the new settings to take place RAW 0A 00 0C Release CDR Reset 4 2 2 2 LMH0318 Register Reset Restore registers default settings RAW FF 04 07 Select Channel Registers RAW 00 0...

Страница 8: ... asserted There could be a need to power down the device even when there is active signal This could be achieved either by disabling ENABLE pin or forcing the signal detect de asserted and thus powering down the selected channel To force IN0 signal detect off RAW FF 04 07 Select Channel Registers RAW 14 40 C0 Force Signal Detect Off for IN0 To force IN1 signal detect off RAW FF 04 07 Select Channe...

Страница 9: ...92 and ST 259 only RAW 0A 0C 0C Initialize CDR State Machine Control RAW 0A 00 0C Release CDR Reset Alternatively the following sequence can be used to disable lock to certain data rates for example 3G RAW FF 04 07 Select Channel Registers RAW A0 00 04 Disable Lock to 3G RAW 0A 0C 0C Reset CDR RAW 0A 00 0C Release CDR Reset 4 2 5 Check Status of LOS Loss Of Signal on Input 1 or Input 0 The LMH0318...

Страница 10: ...d by the transmission media Deterministic jitter due to the ISI Inter Symbol Interference caused by the media can be equalized by the LMH0318 CTLE In the default mode the CTLE boost is determined by register 0x03 The default value of 0x80 h equalizes 10 15 inches PCB FR4 trace loss The user may change register 0x03 to enable different boost settings for different media loss characteristics Table 4...

Страница 11: ...A 44 FF RAW 31 20 60 Enable CTLE Test Mode to optimize eye opening RAW 0A 0C 0C Reset CDR for the new settings to take place RAW 0A 00 0C Release CDR Reset RAW 0C 00 F0 Setup register 0x0C to read lock indication RAW 02 18 18 Wait until bits 4 3 11 b to indicate CDR locked RAR 52 xx FF Read EQ Boost setting and store in xx for normal mode of operation RAW 03 xx FF Save EQ Boost setting in reg 0x03...

Страница 12: ... common measurement performed by the EOM is the horizontal and vertical eye opening The Horizontal Eye Opening HEO represents the width of the post equalized eye at 0 V differential amplitude typically measured in unit intervals or pico seconds The Vertical Eye Opening VEO represents the height of the post equalized eye measured midway between the mean zero crossing of the eye This position in tim...

Страница 13: ... be optioned to cause interrupt if HEO VEO reach a threshold To convert the HEO reading to Unit Interval UI eye opening we need to divide the HEO reading in decimal to 64 HEO Decimal Reg0x27 64 For example if the HEO reading is 0x31 49 decimal then the HEO UI eye opening would be 49 64 0 77UI This means the HEO is about 77 open Similarly VEO has 64 steps as well The chip automatically covers diffe...

Страница 14: ...Unlocked Raw Data Unlocked Mute 10 Locked Reclocked Data Locked Reclocked Data Unlocked Raw Data Unlocked Raw Data 11 Forced Raw Data Forced Raw Data The following can be used to set OUT0 and OUT1 configuration RAW FF 04 07 Select Channel Registers RAW 09 00 20 Allow register 0x1C to control OUT0 and OUT1 configuration RAW 1C 00 0C Mute OUT0 and OUT1 RAW 1C 04 0C Locked OUT0 Reclocked Data OUT1 Re...

Страница 15: ... RAW 1C 00 E0 Set to 0 Mute OUT0 4 2 11 2 4 OUT0 Reclocked Data RAW FF 04 07 Select Channel Registers RAW 09 20 20 Enable Over ride RAW 1C 80 E0 OUT0 Reclocked Data valid only in locked condition 4 2 11 2 5 OUT1 RAW Data RAW FF 04 07 Select Channel Registers RAW 09 20 20 Enable Over ride to control this setting with registers RAW 1E 00 E0 OUT1 RAW Data 4 2 11 2 6 OUT1 Mute When OUT1 is muted the d...

Страница 16: ...lock RAW FF 04 07 Select Channel Registers RAW 09 20 20 Enable over ride RAW 1E A0 E0 Enable 10 MHz on OUT1 4 2 12 Invert OUT1 Data Polarity For ease of layout there may be a need to invert the polarity of the OUT1 differential pair RAW FF 04 07 Select Channel Registers RAW 1E 80 80 Invert OUT1 Polarity 4 2 13 OUT0 and OUT1 Settings The LMH0318 has programmable VOD Voltage Output Differential Pre ...

Страница 17: ...wer up OUT0 4 2 13 3 OUT1 VOD Settings OUT1 VOD settings can have a range of 600 mv to 1300 mv RAW FF 04 07 Select Channel Registers RAW 84 00 70 Set drv_1_sel_vod to 0 570 mVp p RAW 84 20 70 Set drv_1_sel_vod to 2 730 mVp p RAW 84 40 70 Set drv_1_sel_vod to 4 900 mVp p RAW 84 60 70 Set drv_1_sel_vod to 6 1035 mVp p 4 2 13 4 OUT1 De Emphasis Settings There are 15 output de emphasis settings for th...

Страница 18: ...Signal Quality Alert interrupt RAW FF 20 20 Enable interrupt onto LOS pin RAW 0A 0C 0C Reset CDR RAW 0A 00 0C Release CDR Reset so changes will go into effect 4 2 15 Signal Quality Alert VEO Threshold Settings Similar to HEO setting the VEO can also be programmed to cause if VEO drops below a threshold RAW FF 04 07 Select Channel Registers RAW 11 00 20 Enable EOM RAW 32 06 0F Set VEO interrupt thr...

Страница 19: ...iguration c Optional Input Output selection d Optional VOD selection e CDR Reset and Release 5 1 Global Registers Table 5 Global Registers FIELD REGISTER REGISTER NAME BITS DEFAULT R RW DESCRIPTION ADDRESS SMBus Observation Reg_0x00 Share 0x00 SMBus Address Observation 7 SMBUS_addr3 0 R SMBus strap observation 6 SMBUS_addr2 0 R 5 SMBUS_addr1 0 R 4 SMBUS_addr0 0 R 3 Reserved 0 RW 2 Reserved 0 RW 1 ...

Страница 20: ...0 Selects signal detect onto LOS pin 4 Reserved 0 RW 3 Reserved 0 RW en_ch_Access 1 Enables access to channel 2 0 RW registers 0 Enables access to share registers 1 Reserved 0 RW 0 Reserved 0 RW Reset_Channel_Regs Reg_0x00 Channel Reset all Channel Registers to 0x00 Default Values 7 Reserved 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 Rst_regs 1 Reset Channel Registers self 2 0 clearing ...

Страница 21: ...ock_int 1 CDR Lock interrupt 6 0 R 0 No interrupt from CDR Lock signal_det1_int 1 IN1 Signal Detect interrupt 5 0 R 0 No interrupt from IN1 Signal Detect signal_det0_int 1 IN0 Signal Detect interrupt 4 0 R 0 No interrupt from IN0 Signal Detect heo_veo_int 1 HEO_VEO Threshold reached 3 0 R interrupt 0 No interrupt from HEO_VEO cdr_lock_loss_int 1 CDR loss of lock interrupt 2 0 R 0 No interrupt from...

Страница 22: ...ct is asserted 4 0 RW 0 Disable interrupt if IN0 Signal Detect is asserted heo_veo_int_en 1 Enable interrupt if HEO VEO threshold is reached 3 0 RW 0 Disable interrupt due to HEO VEO threshold cdr_lock_loss_int_en 1 Enable interrupt if CDR loses lock 2 0 RW 0 Disable interrupt if CDR loses lock signal_det1_loss_int_en 1 Enable interrupt if there is loss of signal on IN1 1 0 RW 0 Disable interrupt ...

Страница 23: ...rved 0 RW 5 Reserved 0 RW 4 Reserved 0 RW 3 Reserved 0 RW 2 Reserved 0 RW 1 Reserved 0 RW Mr_auto_eq_en_bypass 1 EQ Bypass for 270 Mbps 0 Use EQ Settings in reg0x03 7 0 for 270 Mbps 0 0 RW Note If 0x13 1 mr_eq_en_bypass is set bypass would be set and auto bypass has no significance EQ_SD_CONFIG Reg 0x13 Channel 0x90 Channel EQ Bypass and Power Down 7 Reserved 1 RW sd_0_PD 1 Power Down IN0 Signal D...

Страница 24: ...2 mV 1010 Nominal 5 mV sd_1_refd_sel 0 2 0 RW 1111 Nominal 3 mV 1 Reserved 0 RW 0 Reserved 0 RW EQ_BOOST_OV Reg_0x2D Channel 0x88 EQ Boost Override 7 Reserved 1 RW 6 Reserved 0 RW 5 Reserved 0 RW 4 Reserved 0 RW reg_eq_bst_ov 1 Enable EQ boost over ride See LMH0318 Programming Guide 3 1 RW SNLU183 0 Disable EQ boost over ride 2 Reserved 0 RW 1 Reserved 0 RW 0 Reserved 0 RW CTLE Setting Reg_0x31 Ch...

Страница 25: ...0 0 RW Index 0 Boost Stage 2 bit 0 1 I0_BST3 1 0 RW Index 0 Boost Stage 3 bit 1 0 I0_BST3 0 0 RW Index 0 Boost Stage 3 bit 0 BST_Indx1 Reg 0x41 Channel 0x40 Index1 4 Stage EQ Boost 7 I1_BST0 1 0 RW Index 1 Boost Stage 0 bit 1 6 I1_BST0 0 1 RW Index 1 Boost Stage 0 bit 0 5 I1_BST1 1 0 RW Index 1 Boost Stage 1 bit 1 4 I1_BST1 0 0 RW Index 1 Boost Stage 1 bit 0 3 I1_BST2 1 0 RW Index 1 Boost Stage 2 ...

Страница 26: ..._BST0 0 0 RW Index 5 Boost Stage 0 bit 0 5 I5_BST1 1 0 RW Index 5 Boost Stage 1 bit 1 4 I5_BST1 0 1 RW Index 5 Boost Stage 1 bit 0 3 I5_BST2 1 0 RW Index 5 Boost Stage 2 bit 1 2 I5_BST2 0 0 RW Index 5 Boost Stage 2 bit 0 1 I5_BST3 1 0 RW Index 5 Boost Stage 3 bit 1 0 I5_BST3 0 0 RW Index 5 Boost Stage 3 bit 0 BST_Indx6 Reg 0x46 Channel 0x54 Index6 4 Stage EQ Boost 7 I6_BST0 1 0 RW Index 6 Boost St...

Страница 27: ...10 Boost Stage 0 bit 0 5 I10_BST1 1 1 RW Index 10 Boost Stage 1 bit 1 4 I10_BST1 0 0 RW Index 10 Boost Stage 1 bit 0 3 I10_BST2 1 1 RW Index 10 Boost Stage 2 bit 1 2 I10_BST2 0 0 RW Index 10 Boost Stage 2 bit 0 1 I10_BST3 1 0 RW Index 10 Boost Stage 3 bit 1 0 I10_BST3 0 1 RW Index 10 Boost Stage 3 bit 0 BST_Indx11 Reg 0x4B Channel 0xD5 Index11 4 Stage EQ Boost 7 I11_BST0 1 1 RW Index 11 Boost Stag...

Страница 28: ... 1 0 I14_BST3 0 0 RW Index 14 Boost Stage 3 bit 0 BST_Indx15 Reg 0x4F Channel 0xF9 Index15 4 Stage EQ Boost 7 I15_BST0 1 1 RW Index 15 Boost Stage 0 bit 1 6 I15_BST0 0 1 RW Index 15 Boost Stage 0 bit 0 5 I15_BST1 1 1 RW Index 15 Boost Stage 1 bit 1 4 I15_BST1 0 1 RW Index 15 Boost Stage 1 bit 0 3 I15_BST2 1 1 RW Index 15 Boost Stage 2 bit 1 2 I15_BST2 0 0 RW Index 15 Boost Stage 2 bit 0 1 I15_BST3...

Страница 29: ...b 2 reg_cdr_reset_sm 0 RW 0 Disable CDR Reset if 0x0A 3 1 b 1 Reserved 0 RW 0 Reserved 0 RW CDR_Status Reg 0x0C Channel 0x08 CDR Status Control 7 reg_sh_status_control 3 0 RW Determines what is shown in Reg 0x02 6 reg_sh_status_control 2 0 RW See LMH0318 Programming Guide 5 reg_sh_status_control 1 0 RW SNLU183 4 reg_sh_status_control 0 0 RW 3 Reserved 1 RW 2 Reserved 0 RW 1 Reserved 0 RW 0 Reserve...

Страница 30: ...NTL Reg 0x24 Channel 0x00 0x00 Eye Opening Monitor Control Register 1 Enable Fast EOM mode 7 fast_eom 0 R 0 Disable fast EOM mode 6 Reserved 0 R 1 No zero crossing in the eye diagram get_heo_veo_error_no_hi observed 5 0 R ts 0 Zero crossing in the eye diagram detected get_heo_veo_error_no_o 1 Eye diagram is completely closed 4 0 R pening 0 Open eye diagram detected 3 Reserved 0 R 2 Reserved 0 R 1 ...

Страница 31: ...dec then divide by 3 heo 3 0 R 64 2 heo 2 0 R 1 heo 1 0 R 0 heo 0 0 R VEO Reg 0x28 Channel 0x00 Vertical Eye Opening 7 veo 7 0 R 6 veo 6 0 R 5 veo 5 0 R This is measured in 0 63 vertical steps 4 veo 4 0 R To get VEO in mV read VEO convert 3 veo 3 0 R hex to dec then multiply by 3 125mV 2 veo 2 0 R 1 veo 1 0 R 0 veo 0 0 R Auto_EOM _Vrange Reg 0x29 Channel 0x00 EOM Vrange Readback 7 Reserved 0 RW 6 ...

Страница 32: ... 1 Enable Auto VEO scaling 6 veo_scale 0 RW 0 VEO scaling based on Vrange Setting 0x11 7 6 5 Reserved 1 RW 4 Reserved 1 RW 3 Reserved 0 RW 2 Reserved 0 RW 1 Reserved 1 RW 0 Reserved 0 RW HEO VEO Threshold Reg 0x32 Channel 0x11 HEO VEO Interrupt Threshold 7 heo_int_thresh 3 0 RW 6 heo_int_thresh 2 0 RW Compares HEO value 0x27 7 0 vs threshold 0x32 7 4 4 5 heo_int_thresh 1 0 RW 4 heo_int_thresh 0 1 ...

Страница 33: ...once every 65 ms 0 hv_lckmon_cnt_ms 0 0 RW CDR State Machine Reg 0x6A Channel 0x44 CDR State Machine Control Control 7 INIT_CDR_SM_57 0 RW 6 INIT_CDR_SM_56 1 RW 5 INIT_CDR_SM_55 0 RW 4 INIT_CDR_SM_54 0 RW At power up this register should be set to 0x00 See initialization set up 3 INIT_CDR_SM_53 0 RW 2 INIT_CDR_SM_52 1 RW 1 INIT_CDR_SM_51 0 RW 0 INIT_CDR_SM_50 0 RW SMPTE_Rate_Enable Reg 0xA0 Channe...

Страница 34: ...UT1 00 mr_drv_out_ctrl 0 OUT0 Mute OUT1 Mute 01 OUT0 Locked Reclocked Data Unlocked Raw Data OUT1 Locked Output Clock Unlocked Mute 2 0 RW 10 OUT0 Locked Reclocked Data Unlocked RAW OUT1 Locked Reclocked Data Unlocked Raw 11 OUT0 Forced Raw OUT1 Forced Raw 1 Reserved 0 RW 0 Reserved 0 RW OUT1_Mux_Select Reg 0x1E Channel 0xE9 OUT1 Mux Selection 7 pfd_sel_data_mux 2 1 RW When 0x09 5 1 b OUT0 Mux Sel...

Страница 35: ...sm control 1 0 RW 0 Disable 0x80 0 to override pin sm control sm_drv_0_PD 1 Power down OUT0 0 0 RW 0 OUT1 in normal operating mode OUT1_VOD Reg 0x84 Channel 0x04 OUT1 VOD Control 7 Reserved 0 RW 6 drv_1_sel_vod 2 0 RW OUTDriver1 VOD Setting 000 570 mVDifferential Diff Peak to 5 drv_1_sel_vod 1 0 RW Peak PP drv_1_sel_vod 0 010 730 mV Diff PP 4 0 RW 100 900 mV Diff PP 110 1035 mV Diff PP 3 Reserved ...

Страница 36: ...DESCRIPTION ADDRESS 3 drv_1_dem_range 0 RW Controls de emphasis of 50 Ω Driver 0000 DE Disabled 2 drv_1_dem 2 0 RW 0001 0 2 dB 1 drv_1_dem 1 0 RW 0010 1 8 dB drv_1_dem 0 0 0 RW 0111 11 dB 36 LMH0318 Programming Guide SNLU183 September 2015 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated ...

Страница 37: ...ring the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warranted for the remainder of the original warranty period Replaced EVMs shall be warranted for a new full ninety 90 day warranty period 3 ...

Страница 38: ... by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la rég...

Страница 39: ... connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even with the inputs and outputs kept within the specified allowable ranges some circuit components may have elevated case temperatures These components include but are not limited to linear regulators switching transistors pass transistors cu...

Страница 40: ...F REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED 8 2 Specific Limitations IN NO EVENT SHALL T...

Страница 41: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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