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Setup

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8

SNVU543A – November 2016 – Revised December 2016

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Copyright © 2016, Texas Instruments Incorporated

LM5170-Q1 EVM User Guide

(1)

Jumper pins open.

(2)

Jumper pins closed.

Table 3. Two-Pin Header Settings

HEADER

SIGNAL

PINS

FUNCTION DESCRIPTION

DEFAULT

J2

IOUT1

O

(1)

External IOUT1 termination

C

(2)

Onboard IOUT1 termination

Y

J3

SYNCOUT

O

Enable the fault detection

Y

C

Disable the fault detection disabled

J4

VCC

O

An external 10-V supply as VCC supply

Y

C

The onboard 10-V regulator as VCC supply

J6

ISETD

O

ISETD input disabled

C

ISETD input is enabled

Y

J8

IOUT2

O

External IOUT2 signal termination

C

Onboard IOUT2 signal termination

Y

J14

3.3 V

O

Onboard 3.3-V bias voltage disconnected from the slave EVM

Y

C

Onboard 3.3-V bias voltage feeding the slave EVM

J15

5 V

O

Onboard 5-V bias voltage disconnected from the slave EVM

Y

C

Onboard 5-V bias voltage feeding the slave EVM

J16

IOUT_All

O

Independent channel monitor

Y

C

Combined total monitor in master/slave configuration. Requiring
J25 to be closed too.

J19

10 V

O

10-V bias voltage disconnected from the slave EVM

Y

C

10-V bias voltage feeding the slave EVM

J20

nFAULT

O

Independent master/slave nFAULT signal

Y

C

Combined master/slave nFAULT signal

J22

EN

O

Independent enable control of the master and slave EVMs

Y

C

Combined enable control of the master and slave EVMs

J23

CH1S

O

Independent slave EVM CH-1 enable

Y

C

Combined master/slave channel enable

J24

IOUT1-2

O

Independent channel current monitors

Y

C

Combined dual-channel current monitor

J25

EN1-2

O

Independent channel enable

Y

C

Combined dual-channel enable

J26

DTS

O

Independent DT adjustment input for the slave EVM

Y

C

Combined DT adjustment for both the master and slave EVMs

J27

DT

O

External programmable DT adjustment input

Y

C

Onboard DT setting

J32

OPT/ EN2_slave

O

3- and 4-phase transition disabled

Y

C

3- and 4-phases transition enabled

J33

ILIM

O

External current limit control input

Y

—

Do not close

J34

48VDC Sense

O

Boost analog outer voltage loop control disabled

Y

C

Boost analog outer voltage loop control enabled

J35

12VDC Sense

O

Buck analog outer voltage loop control disabled

Y

C

Buck analog outer voltage loop control enabled

J36

ISETA

O

Analog outer voltage loop control disabled

Y

C

Analog outer voltage loop control enabled

J37

5 V

O

Analog outer voltage loop control disabled

Y

C

Analog outer voltage loop control enabled

Содержание LM5170-Q1 EVM

Страница 1: ...rectional Current Controller Datasheet SNVSAQ6 for detailed technical information of the LM5170 Q1 device Contents 1 Features and Electrical Performance 3 2 Setup 4 3 Test Procedure 12 4 Test Data 14 5 Design Files 19 List of Figures 1 Simplified EVM Schematic 5 2 EVM Board Top View and Layout Partitions 6 3 Bidirectional Converter Bench Setup 11 4 Buck Mode Efficiency vs Input Voltage and Load Cu...

Страница 2: ...ptional Outer Voltage Loop Control Circuit 22 31 EVM Schematic Part 5 Interface Connectors and Configuration Headers 23 32 EVM Top Layer Silkscreen 27 33 EVM Top Layer Copper 28 34 EVM Middle Layer 1 29 35 EVM Middle Layer 2 30 36 EVM Middle Layer 3 31 37 EVM Middle Layer 4 32 38 EVM Middle Layer 5 33 39 EVM Middle Layer 6 34 40 EVM Bottom Layer Copper 35 41 EVM Bottom Layer Silkscreen 36 List of ...

Страница 3: ...pical 1 Current Monitor Accuracy Switching Frequency Standalone Fsw 100 kHz Able to Synchronize to an External Clock from 80 kHz to 120 kHz Maximum Efficiency 97 OVP Threshold 75 V at the 48VDC Port 22 V at the 12VDC Port Synchronous Rectifier Diode Emulation Function Preventing Negative Current Other Convenient Features Optional Onboard Wide VIN LM5118 Q1 Buck Boost Converter as the 10 V Supply O...

Страница 4: ... 2 1 EVM Configurations Figure 2 shows the EVM board top view and circuit layout partitions The EVM has the following ports 48VDC Port Connected to 48 V battery rail 12VDC Port Connected to 12 V battery rail J17 60 Pin Header Interfacing the external control commands or MCU J18 60 Pin Header Interfacing the slave EVM s J17 in a 4 phase system consisting of two EVMs Master Enable Using J17 pin 5 Pr...

Страница 5: ...30 IPK 40 2 k 29 OPT 37 IOUT1 38 IOUT2 9 09 k 10 k 47 OSC 40 2 k 10 nF 10 nF AGND 24 SW1 13 SW2 0 22 µF IOUT1 IOUT2 27 nFAULT PGND 48VDC Port VCC 100 µF 100 µF PGND 470 µF LM5170 Q1 CMMD AND MONITOR C2 C1 CHB1 QH1 QL2 CVCC C5 CIOUT1 CIOUT2 C8 CHB2 C10 CSS CHF1 CCOMP1 CRAMP2 CRAMP1 QH2 QL2 RCS2 RVCCA ROSC RSYNCO RIOUT1 RIOUT2 RIPK ROVPB ROVPA RDT RCOMP1 RRAMP2 RRAMP1 RBRK DHB1 DHB2 18 PGND PGND PGN...

Страница 6: ...www ti com 6 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 2 EVM Board Top View and Layout Partitions ...

Страница 7: ...perature protection in hiccup mode 2 3 Overtemperature protection in latched shutdown J13 SYNC Slave EVM not sync to master EVM Y 1 2 Slave EVM sync to master via J18 2 3 Slave EVM sync to external Clock J21 BIAS Use external 10V supply 1 2 Onboard 10V produced from the 12VDC Port 2 3 Onboard 10V produced from the 48VDC Port Y J28 DIR External DIR control through J17 1 2 Onboard DIR command for bu...

Страница 8: ...e EVM Y C 10 V bias voltage feeding the slave EVM J20 nFAULT O Independent master slave nFAULT signal Y C Combined master slave nFAULT signal J22 EN O Independent enable control of the master and slave EVMs Y C Combined enable control of the master and slave EVMs J23 CH1S O Independent slave EVM CH 1 enable Y C Combined master slave channel enable J24 IOUT1 2 O Independent channel current monitors...

Страница 9: ...g 21 CH2 I CH 2 control connect to the EN2 pin of the IC 23 3 3 V O Output of onboard 3 3 V voltage 25 5 V O Output of onboard 5 V voltage 27 IOUT1 O CH 1 monitor 29 IOUT2 O CH 2 current monitor 31 IOUT1_S O Slave EVM CH 1 monitor in 3 or 4 phases 33 IOUT2_S O Slave EVM CH 2 current monitor in 3 or 4 phases 35 AGND I O Reference GND for control signals 37 PGND O Power ground of the DC DC converter...

Страница 10: ... PWM signal 15 SYNCIN_S I The external clock input for the slave 17 SYNCOUT_S O 3 Slave EVM clock output signal 19 OPT I Interleave angle setting 21 CH2_S I Slave EVM CH 2 control connect to the EN1 pin of the IC 23 3 3 V I Output of onboard 3 3 V voltage 25 5 V I Output of onboard 5 V voltage 27 IOUT1_S O Slave EVM CH 1 monitor in 3 or 4 phases 29 IOUT2_S O Slave EVM CH 2 current monitor in 3 or ...

Страница 11: ...S voltage at 48 V and the current limit at 15 A Note that in Buck Mode operation the HV E load can be turned off and in Boost Mode operation the LV E load can be turned off If the output voltage loop is closed the LV PS can be disconnected in Buck Mode operation In Boost Mode operation the HV PS is required for Boost start up which is limited by the onboard circuit breaker function If the circuit ...

Страница 12: ... disable each channel The channel enable can also be controlled by J29 J30 and J25 ISETA or ISETD The Channel current regulation setting Applying an analog voltage across J17 pins 11 and 12 or J18 pins 11 and 12 or a PWM signal across J17 pins 13 and 14 or J18 pins 13 and 14 the EVM will regulate the channel DC current which is also the power inductor dc current to a level proportional the ISETA v...

Страница 13: ...n 13 or J18 pin 13 7 Dynamically flip the DIR signal state between 0 DIR 1 V and 1 DIR 2 V the EVM will operate in dynamic bidirectional transition mode 8 Perform the test 9 After the tests are done turn off the ISETA or ISETD signal turn off the DIR signal remove the voltage at J17 pin 5 and turn off the E Load HV PS and LV PS 3 4 Operating the EVM With the Onboard Analog Loop Control Circuit 1 J...

Страница 14: ...Current A Efficiency 0 10 20 30 40 50 60 80 82 84 86 88 90 92 94 96 98 100 D001 VIN 24 V VIN 36 V VIN 48 V VIN 60 V Load Current A Efficiency 0 2 4 6 8 10 12 14 80 82 84 86 88 90 92 94 96 98 100 VIN 16 V VIN 12 V VIN 8 V Test Data www ti com 14 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide 4 Test Da...

Страница 15: ...aster Enable Power Up and Shutdown Figure 10 EVM Enable Power Up Sequence Figure 11 EVM Shutdown by nFAULT 4 4 Channel Enable and Disable Figure 12 Buck Mode Enable Figure 13 Boost Mode Enable 4 5 Dual Channel Interleaving Operation Figure 14 Dual Channel Interleaving Operation in Buck Mode 20 A Per Channel Figure 15 Dual Channel Interleaving Operation in Boost Mode 20 A Per Channel ...

Страница 16: ...truments Incorporated LM5170 Q1 EVM User Guide 4 6 ISETA Tracking Figure 16 Inductor Current Tracking Buck Mode Figure 17 Inductor Current Tracking Boost Mode 4 7 Diode Emulation Preventing Negative Currents Figure 18 Diode Emulation During Start Up Figure 19 Diode Emulation During Shutdown Figure 20 Diode Emulation in DCM ...

Страница 17: ...ents Incorporated LM5170 Q1 EVM User Guide 4 8 Dynamic DIR Change Figure 21 Response to Dynamic DIR Change 4 9 Step Load Response Figure 22 Step Load Response Buck Mode 20 A to 50 A Load Step 1A μs Figure 23 Step Load Response Boost Mode 5 A to 10 A Load Step 1A μs 4 10 OVP Figure 24 OVP in Buck Mode Figure 25 OVP in Boost Mode ...

Страница 18: ...com 18 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide 4 11 Output Short Circuit Figure 26 Output Short Circuit Buck Mode ...

Страница 19: ...r 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide 5 Design Files 5 1 Schematics To download the Schematics for the EVM board see the design files at www ti com tool Figure 27 EVM Schematic Part 1 Power Circuit ...

Страница 20: ...les www ti com 20 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 28 EVM Schematic Part 2 Control Circuit ...

Страница 21: ...om Design Files 21 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 29 EVM Schematic Part 3 Bias Supplies ...

Страница 22: ... 22 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 30 EVM Schematic Part 4 Optional Outer Voltage Loop Control Circuit ...

Страница 23: ...23 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 31 EVM Schematic Part 5 Interface Connectors and Configuration Headers ...

Страница 24: ...DA101MLH0S Chemi Con 4 C20 C21 C54 C55 CAP AL 180 µF 50 V SMD PCR1H181MCL1GS Nichicon 18 C22 C23 C24 C25 C26 C27 C28 C29 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 CAP CERM 4 7 µF 100 V X7R 2220 C5750X7R2A475M230KA TDK 1 C38 CAP AL 22 µF 100 V 20 SMD EMVH101ADA220MJA0G Chemi Con 1 C39 CAP CERM 10 µF 100 V X7S C5750X7S2A106M230KB TDK 1 C40 CAP CERM 0 1 µF 100 V X7R 0805 C2012X7R2A104K125AA TDK 1 C40 C...

Страница 25: ...70 Wurth 1 L3 Inductor 47 µH 2 9 A 0 07 Ω SMD MSS1278 473MLB Coilcraft Inductor 47 µH SMD Substitue 784770470 Wurth 8 Q1 Q2 Q3 Q4 Q10 Q11 Q12 Q13 MOSFET N CH 100 V D2PAK TK65G10N1 RQ Toshiba Semiconductor and Storage 4 Q5 Q6 Q8 Q9 MOSFET N CH 60 V 240 A D2PAK IRFS7530 7PPBF International Rectifier 4 Q7 Q16 Q17 Q18 MOSFET N CH 60 V 0 24 A SOT 23 2N7002E T1 E3 Vishay Siliconix 2 Q14 Q15 MOSFET N CH ...

Страница 26: ...ishay Dale 1 R77 RES 2 10 k 1 0 1 W 0603 CRCW06032K10FKEA Vishay Dale 1 R78 RES 4 42 k 1 0 1 W 0603 CRCW06034K42FKEA Vishay Dale 1 R80 RES 24 9 k 1 0 1 W 0603 CRCW060324K9FKEA Vishay Dale 2 R85 R88 RES 20 0 1 0 1 W 0603 CRCW060320R0FKEA Vishay Dale 1 R86 RES 6 81 k 1 0 1 W 0603 CRCW06036K81FKEA Vishay Dale 4 T1 T2 T3 T4 Terminal 70 A Lug CXS70 14 C Panduit 1 U1 Dual Channel 48 V to 12 V Bidirectio...

Страница 27: ...tation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide 5 3 Board Layout The EVM includes various headers for flexible configurations suitable for different applications Figure 32 through Figure 41 show the EVM PCB artwork Figure 32 EVM Top Layer Silkscreen ...

Страница 28: ...esign Files www ti com 28 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 33 EVM Top Layer Copper ...

Страница 29: ...www ti com Design Files 29 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 34 EVM Middle Layer 1 ...

Страница 30: ...Design Files www ti com 30 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 35 EVM Middle Layer 2 ...

Страница 31: ...www ti com Design Files 31 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 36 EVM Middle Layer 3 ...

Страница 32: ...Design Files www ti com 32 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 37 EVM Middle Layer 4 ...

Страница 33: ...www ti com Design Files 33 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 38 EVM Middle Layer 5 ...

Страница 34: ...Design Files www ti com 34 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 39 EVM Middle Layer 6 ...

Страница 35: ...w ti com Design Files 35 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 40 EVM Bottom Layer Copper ...

Страница 36: ...gn Files www ti com 36 SNVU543A November 2016 Revised December 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LM5170 Q1 EVM User Guide Figure 41 EVM Bottom Layer Silkscreen ...

Страница 37: ... page numbers in the current version Changes from Original November 2016 to A Revision Page Changed the test conditions for 48VDC Port input parameter from DIR 1 V to DIR 2 V 4 Changed the test conditions for 12VDC Port input parameter from DIR 2 V to DIR 1 V 4 Changed the test conditions for 48VDC Port output parameter from Buck mode to Boost mode 4 Changed the test conditions for 48VDC Port outp...

Страница 38: ... TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI product...

Страница 39: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments LM5170EVM BIDIR ...

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