Texas Instruments eInfochips TMDXEVM6657L, Техническое справочное руководство, Страница: 75 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 75 / 90
5.6 FPGA Configuration Registers
The TMS320C6657 DSP communicates with the FPGA configuration registers through the SPI interface. These
registers are addressed by memory mapped location and defined by the DSP SPI chip enable setting. The
following tables list the FPGA configuration registers and the respective descriptions.
Table 5.3: C6657 Lite EVM FPGA Pin Description
Memory Map Base Address Memory Map Offset Address Memory
DSP SPI Chip Select 1
0x20BF0000-0x20BF03FF
(TMS320C6657 DSP SPI
Memory Map Address)
0x00-0x3F Configuration Registers
5.6.1 FPGA Configuration Registers Summary
Table 5.4: FPGA Configuration Registers Summary
Address Offset Definition
Attribute (R/W)
(RO : Read-Only)
Default Value
00h FPGA Device ID (Low Byte) RO 04h
01h FPGA Device ID (High Byte) RO 80h
02h FPGA Revision ID (Low Byte) RO **
03h FPGA Revision ID (High Byte) RO 00h*
04h BM GPI Status (Low Byte) RO ----
05h BM GPI Status (High Byte) RO ----
06h DSP GPI Status (Low Byte) RO ----
07h DSP GPI status (High Byte) RO ----
08h Debug LED R/W 00h
09h MMC Control RO ----
0Ah PHY Control R/W 03h
0Bh Reset Buttons Status RO 00h
0Ch Miscellaneous - 1 R/W 1Ch
0Dh Miscellaneous - 2 RO --
0Eh
FPGA FW Update SPI Interface
Control Register
R/W 00h
0Fh Scratch Register R/W 00h
10h CLK-GEN 2 Control Register R/W 00h
11h
CLK-GEN 2 Interface Clock
Setting
R/W 03h
13h~12h Reserved 0s
14h CLK-GEN 2 Command Byte 0 R/W 00h
15h CLK-GEN 2 Command Byte 1 R/W 00h