Texas Instruments eInfochips TMDXEVM6657L, Техническое справочное руководство, Страница: 68 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 68 / 90
DSP_TIMI0 O
DSP Timer 0 Clock: FPGA provides a 24MHz clock
to the DSP timer 0 input. During EVM Power-on or
RESETFULLZ asserted period, FPGA will drive the
PCIESSEN switch state to DSP for latching.
DSP_TIMI1 O
DSP Timer 1 Clock: FPGA provides a 24MHz clock
to the DSP timer 1 input. During EVM Power-on or
RESETFULLZ asserted period, FPGA will drive the
PCIESSEN switch state to DSP for latching.
DSP_TIMO0 I
DSP_TIMO1 I
DSP_VCL_1 (RFU) I DSP Smart Reflex I2C Clock
DSP_VD_1 (RFU) I/O DSP Smart Reflex I2C Clock
PCA9306_EN O
PCA9306 Enable: Used to enable DSP Smart Reflex
I2C buffer function.
NAND_WP# O
NAND Flash Write Protect: Used to control NAND
flash write-protect function.
NOR_WP# O
NOR Flash Write Protect: Used to control NOR
flash write-protect function.
EEPROM_WP O
EEPROM Write Protect: Used to control EEPROM
write-protect function.
PCIESSEN I
PCIe Subsystem Enable: Used for PCIESSEN
switch input.
USER_DEFINE I
User Defined Switch: Reserved for user defined
switch input.
MUX_SEL O
PCIe Clock Multiplexor Input selection: Selects
PCIE reference clock from CDCE62005 or AMC edge
connector. The default is from CDCE62005. Also,
when PCIe boot mode is selected, SW5.3 controls
the default level for the register and this clock select.
MUX_PD# O
PCIe Clock Multiplexor Power Down: Used to
control PCIe mux
PD# pin, it‟s de-asserted after
VCC1V5 valid.
MUX_OE O
PCIe Clock Multiplexor Output Enable: Enables
the output of PCIe mux.
VID_OE# O
Smart-Reflex VID Enable: Enables the output of
Smart-Reflex VID from DSP to UCD9222.
XDS560_IL O XDS560 IL: XDS560 IL control signal
FPGA JTAG TAP Control Port:
JTAG_FPGA_TCK I FPGA JTAG Clock Input
JTAG_FPGA_TDI I FPGA JTAG Data Input
JTAG_FPGA_TDI O FPGA JTAG Data Output
JTAG_FPGA_TMS I FPGA JTAG Mode Select Input
JTAG_FPGA_RST# I FPGA JTAG Reset (RFU)
5.3 Sequence of operation
This section describes the FPGA sequence of operation on the EVM. It contains:
5.3.1 Power-On Sequence
5.3.2 Power Off Sequence