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Technical Reference Manual
TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 58 / 90
4.2.2 VCC3V3_AUX and VCC1V5 Design
The
VCC3V3_AUX
and
VCC1V5
power rails are regulated by two TI 6A Synchronous Step
Down SWIFT™
Converters, TPS54620, to supply the peripherals and other power sources and the DSP DDR3 EMIF and DDR3
memory chips respectively.
TPS54620
C = 22uF x 1
100nF x 1
VCC3V_AUX
L = 2.2uH
Over all tolerance 5%,
DC tolerance is 2.5%
K
IND
= 0.3
Figure 4.4: VCC3V3_AUX Design on C6657 Lite EVM
Output Capacitor Calculation
C
out(min1)
= (2*
∆I
out
) / (F
sw
*
∆V
out
)
= (2*1) / (900kHz*0.0825)
≈ 2.69uF
C
out(min2)
= 1/(8*f
sw
)*I
ripple
/V
ripple
= 1/(8*900kHz)*0.3/0.033
≈ 1.26uF
Reference Capacitor = 22uF + 100nF
Inductor Calculation
L = ((V
in(max)
- V
out
)/(I
out
* K
ind
)) * (V
out
/(V
in(max)
* F
sw
))
= ((12.5 - 3.3)/(3 * 0.3) * (3.3 / (12.5 * 900kHz))
= ((9.2/(3 * 0.3) * (3.3 / (11.25M))
= (10.22) * (0.29u)
≈ 2.96uH
Reference Inductor = 2.2uH
TPS54620
C = 100uF x 1
22uF x 1
VCC1V5
L = 1.2uH
Figure 4.5: VCC1V5 Power Design on C6657 Lite EVM
Over all tolerance 5%,
DC tolerance is 2.5%
K
IND
= 0.3
Output Capacitor Calculation
C
out(min)
= (2*
∆I
out
) / (F
sw
*
∆V
out
)
= (2*1)/(900kHz*0.075)
≈ 29.62uF
C
out(min2)
= 1/(8*f
sw
)*I
ripple
/V
ripple
= 1/(8*900kHz)*0.2/0.015
≈ 1.85uF
Reference Capacitor = 100uF + 22uF
Inductor Calculation
L = ((V
in(max)
- V
out
)/(I
out
* K
ind
)) * (V
out
/(V
in(max)
* F
sw
))
= ((12.5 - 1.5)/(2 * 0.3)) * (1.5 / (12.5*900kHz))
= (11/0.6) * (1.5 / (11.25M))
= (18.33) * (0.1333u)
≈ 2.44uH
Reference Inductor = 1.2uH
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