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5 Schematics

5.1 Main Block Schematic

GND

GND

GND

XO

0

R26

1

2

3

4

5

J7

GND

XI
XO

GND

TRD_N

TRD_P

LED_0
LED_1

1

2

3

4

5

J8

GND

0

R31

CLKOUT

CLKOUT

INT

MDIO
MDC

DP83TC812_RESET_N

2

1

D4

2

1

D3

+3V3

GND

2

1

D2

GND

LED_1

2.49k

R1

2.49k

R5

2.49k

R16

1
2
3

J2

LED_0

VDDA3P3

10uF

C20

0.1uF

C14

0.1uF

C22

0.1uF

C16

10uF

C11

10uF

C19

VDDIO

VDDA3P3

10uF

C25

+3V3

+3V3

+1V0

GND

GND

GND

Vin

0

R17

0

R19

2.2k

R12

2.2k

R3

2.2k

R7

GND

INT

INH

INH

VDDIO1

VDDIO

VDDMAC

50V
0.1uF

C29

XI

1

J6

TSW-101-07-G-S

1

J4

TSW-101-07-G-S

867_TX_CTRL

867_TX_CLK

22

R78

22

R79

812_RX_CTRL

812_RX_CLK

812_TX_CLK

812_TX_CTRL

812_TX_D3

812_TX_D2

812_TX_D0

812_TX_CLK

812_TX_CTRL

812_TX_D1
812_TX_D2
812_TX_D3

812_TX_D1

812_TX_D0

2.49k

R95

812_RX_D2

GND

10uF

C24

GND

100

R97

0.1uF

C18

0

R98

GND

GND

50V
0.1uF

C33

50V
0.1uF

C34

+3V3

2.2k

R101

2.2k

R102

VDDIO

0

R100

+3V3

1.00k

R28

VDDMAC

VDDIO1

VDDMAC

VDD1P0_1

VDD1P0_2

VDD1P0_1

VDD1P0_2

Sleep Supply

MDC

1

INT

2

RESET

3

XO

4

XI

5

LED_1/GPIO_1

6

VSLEEP

7

WAKE

8

NC

9

INH

10

VDDA

11

TRD_P

12

TRD_M

13

RX_ER

14

RX_DV/CRS_DV/RX_CTRL

15

CLKOUT/GPIO_2

16

GND_ESC

17

GND_ESC

18

NC

19

NC

20

NC

21

VDDMAC

22

RX_D3

23

RX_D2

24

RX_D1

25

RX_D0

26

RX_CLK

27

TX_CLK

28

TX_EN/TX_CTRL

29

TX_D3

30

TX_D2

31

TX_D1

32

TX_D0

33

VDDIO

34

LED_0/GPIO_0

35

MDIO

36

GND

37

DP83TC812R-Q1

U1

VSLEEP

867_TX_D2
867_TX_D3

22

R6

22

R8

867_TX_D0
867_TX_D1

22

R2

22

R4

812_RX_D0
812_RX_D1
812_RX_D2
812_RX_D3

2.2k

R10

GND

1
2
3

J10

TSW-103-07-G-S

WAKE_812

VSLEEP

VDDMAC

1

2

J1

VDDMAC_1P8

VDDMAC_2P5

1

2

J3

1

2

J5

R11

812

720

811

R100

R17

R19

R96

R11

DNP

DNP

DNP

DNP

DNP

DNP

DNP

DNP

VSLEEP

GND

VDDMAC

1

2

J23

How to Con

gure Between DP83TC812, DP83TC811, DP83TG720

10uF

C9

0.1uF

C21

0.01uF

C26

2.2uF

C13

GND

0.1uF

C32

0.01uF

C96

2.2uF

C27

GND

0.01uF

C97

2.2k

R13

VDDMAC

812_RX_ER

812_RX_ER

IN

1

EN

2

GND

4

DNC

5

PAD

7

OUT

6

GND

3

TPS7B8133QDRVRQ1

U10

10uF

C98

0.1uF

C99

0.047uF

C100

GND

25V

470nF

C1

1

2

L2

BLM18KG601SH1

1

2

L4

BLM18KG601SH1

0

L3

10.0k

R120

10.0k

R9

1
3

4

2

G
G

Y1

25V

470nF

C10

25V

470nF

C12

10nF

C15

10nF

C17

10nF

C23

22pF
50V

C30

22pF
50V

C31

Figure 5-1. Main Schematic

www.ti.com

Schematics

SNLU292A – NOVEMBER 2020 – REVISED MARCH 2022

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DP83TC812EVM-MC User's Guide

9

Copyright © 2022 Texas Instruments Incorporated

Содержание DP83TC812EVM-MC

Страница 1: ...History 2 2 Introduction 3 2 1 Key Features 3 2 2 Operation Quick Setup 4 3 Board Setup Details 7 3 1 Block Diagram 7 3 2 Configuration Options 7 4 Definitions 8 5 Schematics 9 5 1 Main Block Schemat...

Страница 2: ...10 Figure 5 3 Power Schematic 11 Figure 5 4 AFE Schematic 12 Figure 5 5 Comms Schematic 13 Figure 5 6 Hardware Schematic 14 Figure 6 1 Top Overlay 15 Figure 6 2 Bottom Overlay 16 1 Revision History NO...

Страница 3: ...o 100BASE TX IEEE802 3bw Compliant IEEE802 3u Compliant RGMII Back to Back Configuration On board MSP430F5528 USB 2 MDIO Support Status LEDs DP83TC812 Link Link Activity DP83822 Link RJ 45 Power on In...

Страница 4: ...D3P3 and VDD1P0 Place shunt on VDDMAC This supply can have adjustable voltages depending on location of shunt J1 for 3 3V operation J3 for 1 8V operation J5 for 2 5V operation Place shunts on J23 and...

Страница 5: ...right most pin Cross connection rewrok required for Rev A board not required for Rev B current board Figure 2 5 On board MSP connections for MDIO and MDC 2 2 2 2 Downloading USB2MDIO for SMI The on bo...

Страница 6: ...emonstrated in figure below Slave Mode Place shunt across pins 2 and 3 of J2 Figure 2 6 DP83TC812 configured as Master 2 2 4 Wake Selection DP83TC812 Place shunt in PU position at WAKE header shown to...

Страница 7: ...RGMII Straps CLKOUT MSP430F5528 USB2MDIO USB MDIO MDC RGMII 1 0V LDO Figure 3 1 DP83TC812EVM MC Block Diagram 3 2 Configuration Options 3 2 1 Clock Configuration Onboard Clock The onboard crystal is...

Страница 8: ...Data Clock RGMII Reduced Gigabyte Media Independent Interface SFD Start of Frame Detection VDDA Analog Core Supply Rail VDDIO Digital Supply Rail PD Pull down PU Pullup MC Micro controller Definition...

Страница 9: ...14 RX_DV CRS_DV RX_CTRL 15 CLKOUT GPIO_2 16 GND_ESC 17 GND_ESC 18 NC 19 NC 20 NC 21 VDDMAC 22 RX_D3 23 RX_D2 24 RX_D1 25 RX_D0 26 RX_CLK 27 TX_CLK 28 TX_EN TX_CTRL 29 TX_D3 30 TX_D2 31 TX_D1 32 TX_D0...

Страница 10: ...1uF C67 TD_A_P TD_A_N TD_B_P TD_B_N TD_C_P TD_C_N TD_D_P TD_D_N 0 R38 LED21 470 R32 470 R34 LED11 LED01 2 49k R33 GND867 GND 0 01 F 1kV C36 1V0_867 2V5_867 1 0M R35 1V0_REG 1V0_867 2V5_867 867_TX_CLK...

Страница 11: ...LT1G 2 2k R66 1V0 TP8 1502 2 TP9 1502 2 2 2k R61 2 2k R62 IN 1 IN 2 PG 3 BIAS 4 EN 5 GND 6 SS 7 FB 8 OUT 9 OUT 10 PAD 11 TPS74701DRCR U7 25V 1uF C86 GND 3V3_REG 50V 0 1uF C82 50V 0 1uF C88 4 42k R68 1...

Страница 12: ...1 00k R110 1 00k R109 1 0M R115 D1 EZAEG3W11AV D7 EZAEG3W11AV GND 1 2 S 1 S 2 S 3 S 4 S 5 S 6 J11 9 2304372 1 GND812 CON2_P CON2_N GND 1 00k R112 1 00k R111 100k R113 100k R114 1 2 3 4 200 H L1 100nF...

Страница 13: ...R D22 HSMF C165 GND GND 470 R27 470 R99 P1 7 P1 6 P1 7 P1 6 SW1 SW1 SW2 SW3 SW4 SW2 SW3 SW4 INT INH 6 3 1 8 2 7 5 4 S1 219 4LPST P6 0 CB0 A0 1 P6 1 CB1 A1 2 P6 2 CB2 A2 3 P6 3 CB3 A3 4 P6 4 CB4 A4 5 P...

Страница 14: ...e MCU wiring Pin 11 18 50 006 Change MCU MDIO wiring LOGO PCB Texas Instruments FID1 Fiducial FID5 Fiducial FID2 Fiducial FID3 Fiducial FID6 Fiducial FID4 Fiducial SH J1 M7582 05 SH J2 M7582 05 SH J3...

Страница 15: ...6 Layout Figure 6 1 Top Overlay www ti com Schematics SNLU292A NOVEMBER 2020 REVISED MARCH 2022 Submit Document Feedback DP83TC812EVM MC User s Guide 15 Copyright 2022 Texas Instruments Incorporated...

Страница 16: ...Figure 6 2 Bottom Overlay Schematics www ti com 16 DP83TC812EVM MC User s Guide SNLU292A NOVEMBER 2020 REVISED MARCH 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated...

Страница 17: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Страница 18: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Страница 19: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Страница 20: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Страница 21: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Страница 22: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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