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Figure 4-6. DLP Composer - Flash Blocks
Table 4-1. Top Level Flash Structure
DATA
ADDRESS
LENGTH
FPGA Configuration
0x0
0x838DC
Flash Information
0x83900
Variable
Default Configuration (Defconfig)
Variable
Variable
Sequence 1
Variable
0x1000
Sequence 2
Variable
0x1000
Sequence …
Variable
0x1000
Sequence n
Variable
0x1000
Video / Image 1
Variable
Variable
Video / Image 2
Variable
Variable
Video / Image …
Variable
Variable
Video / Image n
Variable
Variable
FPGA Configuration
The FPGA configuration block is always located at address 0x0, and is always a fixed size of 0x838DC
bytes. This size is derived from the Xilinx XA7S15 specification for maximum configuration length. See
the Xilinx UG470 (https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf) for
additional details.
Flash Information
The flash information block provides metadata regarding the contents of the flash. This is intended to allow an
external MCU or software tool understand the contents of the flash. For example, it defines the locations of the
Software
DLPU106A – MARCH 2021 – REVISED OCTOBER 2021
DLP3021LEQ1EVM Evaluation Module
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