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1.4
Software Installation
1.5
Hardware Configuration
Overview
All necessary software to operate the serial interface is provided on the enclosed CD-ROM.
1. Insert the CD-ROM into the computer to be used to operate the serial interface.
2. Unzip the contents of the DAC5686SPI_Installv1p1.zip into the C:\temp directory on the PC.
3. Run the file called setup.exe in the C:\temp\Installer directory.
4. The software will install the appropriate files to the C:\Program Files\TI.fdr directory.
5. Once the installation is complete, the computer should be rebooted. The software is launched by
running
C:\ProgramFiles\TI.fdr\DAC5686_SPI\DAC5686_SPI.exe.
A shortcut for that program can be created and placed on the desktop or any other relevant location. See
, DAC5686 EVM Operational Procedure, for instructions on operating the serial interface
software.
The DAC5686 EVM can be set up in a variety of configurations to accommodate a specific mode of
operation. Before starting evaluation, the user should decide on the configuration and make the
appropriate connections or changes. The demonstration board comes with the following factory-set
configuration:
•
Differential clock mode using transformers T3 and T4. Input single-ended clocks are required at J3 and
J4.
•
Transformer-coupled outputs using transformers T1 and T2.
•
The converter is set to operate with internal reference. Jumper W1 is installed between pins 2 and 3.
•
Full-scale output current set to 20 mA through RBIAS resistor R1.
•
The DAC5686 output is enabled (sleep mode disabled).
•
TXENABLE is set high to enable the DAC5686 device to process data.
•
Internal PLL disabled. Jumper W3 is installed between pins 2 and 3.
•
Input data level is set to +3.3VDC. Jumper W2 is installed between pins 1 and 2.
To prepare the DAC5686 EVM for evaluation, connect the following:
1. 3.3 V to J7 and the return to J9.
2. 1.8 V to J8 and the return to J10.
3. Provide a single-ended, 300-mV
PP
, 0-V offset sine-wave signal to SMA connector J3 (CLK1) if the
internal PLL is to be used. Connect this signal to SMA connector J4 (CLK2) if the PLL is disabled. A
second sine-wave source is required only for dual clock mode. In this mode, the signal on CLK1 is
used to clock data into the DAC5686 and the signal on CLK2 is used to clock the internal DAC. CLK1
and CLK2 must be phase-aligned for this option to work properly. In order to preserve the specified
performance of the DAC5686 converter, the clock sources must feature very low jitter. Using a clock
with a 50% duty cycle gives optimum dynamic performance.
4. Use a digital test pattern generator with 50-
Ω
outputs to provide 3.3-V CMOS logic level inputs to
connectors J13 and J14. Adjust the digital inputs to provide the proper setup and hold times at the
DAC5686 inputs. See the DAC5686 data sheet (
) for timing information.
5. Connect one end of the supplied serial interface cable to the parallel port of a PC. Connect the other
end of the cable to J1 on the EVM.
6. The DAC5686 outputs can be monitored using SMA connector J5 for IOUTA and SMA connector J19
for IOUTB.
DAC5686 EVM
6
SLWU006E – December 2004 – Revised March 2007
