Circuit Function
3-4
3.1.4
Internal Reference Operation
The full-scale output current is set by applying an external resistor (R1)
between the BIASJ pin of the DAC5674 and ground. The full-scale output
current can be adjusted from 20 mA down to 2 mA by varying R1 or changing
the externally applied reference voltage. The full-scale output current,
IOUT
FS
, is defined as follows:
IOUT
FS
= 32
×
(V
EXTIO
/R1)
where V
EXTIO
is the voltage at pin EXTIO. This voltage is 1.2 V typical when
using the internally provided bandgap reference voltage source.
3.1.5
External Reference Operation
The internal reference can be disabled and overridden by an external
reference by connecting a voltage source to terminal TP2 (EXT_I/O) and
connecting EXTLO to AVDD. The specified range for external reference
voltages should be observed (see the DAC5674 data sheet (SLWS148) for
details).
3.1.6
Sleep Mode
The DAC5674 EVM provides a means of placing the DAC5674 into a
power-down mode. This mode is activated by placing jumper W3 between pins
2 and 3.
3.1.7
Filter Control
The DAC5674 has two inputs, HP1 and HP2, which control the internal
interpolation filters (FIR1 and FIR2) mode of operation. When these inputs are
set to a logic high, the filters are configured for high-pass response. When set
to a logic low, the filters are configured for low-pass response. A third input,
X4, allows the user to bypass Interpolation Filter 1. When X4 is set to a logic
low, Filter 1 is bypassed. See the data sheet (SLWS148) for more information.
3.1.8
PLL Divider Control
The DAC5674 has two inputs, DIV0 and DIV1, which control the internal PLL
prescaler divide ratio setting. These two signals, along with the three filter
control signals, are all controlled by DIP switch S2 on the EVM. All control
signals are in the logic low level when the DIP switch is in the closed position.
See the data sheet (SLWS148) for more information.
Содержание DAC5674 EVM
Страница 1: ...DAC5674 EVM September 2003 Wireless Infrastructure Products User s Guide SWRU007 ...
Страница 6: ...Contents vi Figures 2 1 Top Layer 1 2 2 2 2 Ground Plane 2 3 2 3 Power Plane 2 3 2 4 Bottom Layer 2 4 ...
Страница 10: ...1 4 ...
Страница 13: ...PCB Layout 2 3 PCB Layout and Parts List Figure 2 2 Layer 2 Ground Plane Figure 2 3 Layer 3 Power Plane ...
Страница 14: ...PCB Layout 2 4 Figure 2 4 Bottom Layer ...
Страница 21: ...4 1 Schematics Schematics This chapter contains the EVM schematic diagrams Chapter 4 ...