7.3 Feature Description
7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
The DACx300x devices consist of a string architecture with a voltage-output amplifier, as well as an external FB
pin and a voltage-to-current converter for each channel.
shows the DAC architecture within the block
diagram that operates from a 1.8-V to 5.5-V power supply. The DAC has an internal voltage reference of 1.21 V.
Optionally, use an external reference on the VREF pin, or use the power supply as a reference. Voltage output
mode uses one of these three reference options. Current output mode uses an internal band gap to generate the
current outputs. Both the voltage- and current-output modes support multiple programmable output ranges.
The DACx300x devices support Hi-Z output when VDD is off, maintaining a very low leakage current at the
output pins with up to 1.25 V of forced voltage. The DAC output pin also starts up in high-impedance mode
by default, making these devices an excellent choice for voltage margining and scaling applications. To change
the power-up mode to 10 kΩ-GND or 100 kΩ-GND, program the corresponding VOUT-PDN-X field in the
COMMON-CONFIG register and load these bits in the device NVM.
The DACx300x devices support an independent comparator mode for each channel. The respective FBx
pin acts as an input for the comparator. The DAC architecture supports inversion of the comparator output
using register settings. The comparator outputs can be push-pull or open-drain. Comparator mode supports
programmable hysteresis using the
margin-high
and
margin-low
register fields, latching comparator, and window
comparator. The comparator outputs are internally accessible by the device.
The DACx300x devices include a
smart
feature set to enable
processor-less
operation and high-integration. The
NVM enables a predictable start-up. In the absence of a processor or when the processor or software fails, the
GPIO triggers the DAC output without the I
2
C interface. The integrated functions and the FBx pin enable PWM
output for control applications. The FBx pin enables this device to be used as a programmable comparator. The
digital slew-rate control and the Hi-Z power-down modes enable a hassle-free voltage margining and scaling
function.
7.3.2 Digital Input/Output
The DACx300x have four digital IO pins that include I
2
C, SPI, PMBus, and GPIO interfaces. These devices
automatically detect I
2
C and SPI protocols at the first successful communication after power-on, and then
connect to the detected interface. After an interface protocol is connected, any change in the protocol is ignored.
The I
2
C interface uses the A0 pin to select from among four address options. The SPI interface is a 3-wire
interface by default. No readback capability is available in this mode. The GPIO pin can be configured in the
register map and then programmed in to the NVM as the SDO pin. The SPI readback mode is slower than the
write mode. The programming interface pins are:
• I
2
C: SCL, SDA, A0
• SPI: SCLK, SDI, SYNC, SDO/GPIO
The GPIO can be configured as multiple functions other than SDO. These are LDAC, PD, STATUS, PROTECT,
FAULT-DUMP, and RESET. All the digital pins are open-drain when used as outputs. Therefore, all the output
pins must be pulled up to the desired IO voltage using external resistors.
DAC53001, DAC53002, DAC63001, DAC63002
SLASF48 – MAY 2022
Copyright © 2022 Texas Instruments Incorporated
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