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Features
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General Description
Features
www.ti.com
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Easy-to-use evaluation board to generate low-phase noise clocks up to 1.5 GHz
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Easy device programming via host-powered USB port
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Fast configuration through provided graphical user interface (GUI) software interface
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Total board power provided either through USB port or separate 3.3 V and ground connections.
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Single-ended or differential input reference clock
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Crystal filter on output readily available for clocking high-speed analog-to-digital converters, if needed.
Figure 1. CDCE72010EVM Board
The CDCE72010 is a high-performance, low-phase noise clock synchronizer and jitter cleaner. It has one
main universal VCO/VCXO input buffer and an auxiliary universal input buffer. Either Input can drive the
outputs and/or the feedback path to the PFD. The maximum VCXO/VCO input frequency is 1.5 GHz. It
provides support for two redundant input references and using its on-chip PLL architecture can provide up
to ten differential or 20 single-ended low jitter outputs.
The CDCE72010 supports two reference inputs, which can be differential or single-ended. It also provides
two VCXO inputs, which can drive up to ten outputs.
The CDCE72010 then can be programmed through the SPI interface using the evaluation module (EVM)
programming GUI.
The evaluation module (EVM) is designed to demonstrate the electrical performance of the device.
This fully assembled and factory-tested evaluation board allows complete validation of all device functions.
For optimum performance, the board is equipped with 50-
Ω
SMA connectors and well-controlled 50-
Ω
impedance microstrip transmission lines.
1.5-GHz Low-Phase Noise Clock Evaluation Board
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SLAU250 – May 2008