CC1000
SWRS048A Page 16 of 55
11. Signal interface
The signal interface consists of DIO and
DCLK and is used for the data to be
transmitted and data received. DIO is the
bi-directional data line and DCLK provides
a synchronous clock both during data
transmission and data reception.
The
CC1000
can be used with NRZ (Non-
Return-to-Zero) data or Manchester (also
known as bi-phase-level) encoded data.
CC1000
can also synchronise the data from
the demodulator and provide the data
clock at DCLK.
CC1000
can be configured for three
different data formats:
Synchronous NRZ mode.
In transmit
mode
CC1000
provides the data clock at
DCLK, and DIO is used as data input.
Data is clocked into
CC1000
at the rising
edge of DCLK. The data is modulated at
RF without encoding.
CC1000
can be
configured for the data rates 0.6, 1.2, 2.4,
4.8, 9.6, 19.2, 38.4 or 76.8 kbit/s. For 38.4
and 76.8 kbit/s a crystal frequency of
14.7456 MHz must be used. In receive
mode
CC1000
does the synchronisation
and provides received data clock at DCLK
and data at DIO. The data should be
clocked into the interfacing circuit at the
rising edge of DCLK. See Figure 7.
Synchronous Manchester encoded mode.
In transmit mode
CC1000
provides the data
clock at DCLK, and DIO is used as data
input. Data is clocked into
CC1000
at the
rising edge of DCLK and should be in NRZ
format. The data is modulated at RF with
Manchester code. The encoding is done
by
CC1000
. In this mode
CC1000
can be
configured for the data rates 0.3, 0.6, 1.2,
2.4, 4.8, 9.6, 19.2 or 38.4 kbit/s. The 38.4
kbit/s rate corresponds to the maximum
76.8 kBaud due to the Manchester
encoding. For 38.4 and 76.8 kBaud a
crystal frequency of 14.7456 MHz must be
used. In receive mode
CC1000
does the
synchronisation and provides received
data clock at DCLK and data at DIO.
CC1000
does the decoding and NRZ data
is presented at DIO. The data should be
clocked into the interfacing circuit at the
rising edge of DCLK. See Figure 8.
Transparent Asynchronous UART mode.
In transmit mode DIO is used as data
input. The data is modulated at RF without
synchronisation or encoding. In receive
mode the raw data signal from the
demodulator is sent to the output. No
synchronisation or decoding of the signal
is done in
CC1000
and should be done by
the interfacing circuit. The DCLK pin is
used as data output in this mode. Data
rates in the range from 0.6 to 76.8 kBaud
can be used. For 38.4 and 76.8 kBaud a
crystal frequency of 14.7456 MHz must be
used. See Figure 9.
11.1 Manchester encoding and
decoding
In the
Synchronous Manchester encoded
mode
CC1000
uses Manchester coding
when modulating the data. The
CC1000
also performs the data decoding and
synchronisation. The Manchester code is
based on transitions; a “0” is encoded as a
low-to-high transition, a “1” is encoded as
a high-to-low transition. See Figure 10.
The
CC1000
can detect a Manchester
decoding violation and will set a
Manchester Violation Flag when such a
violation is detected in the incoming
signal. The threshold limit for the
Manchester Violation can be set in the
MODEM1
register. The Manchester
Violation Flag can be monitored at the
CHP_OUT (LOCK) pin, configured in the
LOCK
register.
The Manchester code ensures that the
signal has a constant DC component,
which is necessary in some FSK
demodulators. Using this mode also
ensures compatibility with CC400/CC900
designs.
