Application
When polling and balancing, the GUI can communicate with multiple bq76PL455EVMs in a stacked
configuration and log the data received from these evaluation modules to log files stored on the PC, but
the GUI allows data from only a single bq76PL455EVM to be viewed in real time. To switch the real time
view to another bq76PL455EVM, polling and balancing must be stopped, and the user must select a new
evaluation module address from the
Board Address
pull-down menu on the
Setup
tab, then re-enable
polling or balancing.
4.7
Fault
When a fault condition is detected, the bq76PL455A-Q1 communicates the fault back to the host PC on
the FAULT pin. Faults from evaluation modules higher in the daisy chain stack are communicated to the
bottom (that is, lowest address) evaluation module using the FAULT ±differential signal pairs on the J5 -
Diff Comm High and J4 - Diff Comm Low connectors. In the case of the bottom bq76PL455A-Q1, the
single-ended active low FAULT signal is driven low whenever a fault is detected. Since a single virtual
FAULT line is shared by all bq76PL455A-Q1 devices, in a user application the FAULT line going low
should trigger the system controller to start sending commands to discover which bq76PL455A-Q1
detected the fault and understand the nature of that fault so it can take appropriate action.
Currently, the daisy-chained FAULT signal terminates at the lowest evaluation module and the line status
is measured at pin 2 of the J3 - Serial connector. Additionally, a Flt-N test pin is also provided. The GUI
automatically polls the fault registers of thebq76PL455A-Q1 to show current status of all unmasked faults.
4.8
Wake and Power Down
Thebq76PL455A-Q1 has two power states, On (powered up) and Off (powered down). The power state is
controlled by a hardware wake signal and a “wake up tone” on the differential twisted pair communications
link between multiple evaluation modules. In single-ended mode, the bq76PL455A-Q1 uses the WAKEUP
signal (pin 49) as the wake input. When this pin on the bq76PL455A-Q1 is driven high (using an inverted
signal on the J3 - Serial connector), the bottom module in a daisy chain configuration powers on and
generates a “wake up tone”. This tone is sent to other modules via the differential communication bus.
This in turn causes all modules connected to the differential bus to also power on. To power down, the
POWER_DOWN bit in the Device Control Register (address 11) is set by sending a Broadcast Command
to the all bq76PL455A-Q1 devices on the stack while the WAKEUP pin is low on the bottom module.
4.9
Power Supplies
The bq76PL455EVM is powered from the top of the cell stack being monitored and balanced, which may
range from 16 V–79.2 V. Although several options exist to post-regulate this high voltage supply down the
bq76PL455A-Q1’s integrated linear voltage regulator, the bq76PL455EVM implements a simple drop-
down voltage divider. This provides the best low noise performance at the expense of higher
bq76PL455EVM current compared to an implementation in which a switching buck converter is used. A
switching buck converter optimizes efficiency, but compromises noise performance.
The bq76PL455A-Q1 linear voltage controller uses an external NPN power transistor to regulate a 5.3-V
output supply at VP1. The VP1 supply then drives the VDIG digital supply on the bq76PL455A-Q1. A
separate external VIO supply line into the bq76PL455A-Q1 is provided by the PC host via pin 3 on the J3
- Serial connector. Although it is possible to externally supply the VDIG digital supply, it is not
recommended to do so on the bq76PL455EVM.
The bq76PL455A-Q1 also produces a regulated 1.8-V supply for internal use and a 2.5-V reference for
use by the integrated 14-bit ADC. There is no external (pin) access to the 1.8-V supply.
9
SLUUBA7A – April 2015 – Revised July 2015
bq76PL455EVM and GUI User Guide
Copyright © 2015, Texas Instruments Incorporated
