Control Register Demonstration
4.2.1
STATUS: 0x00
Bit 0 is the Power On Reset Flag (POR). It is set on a each power-up and wake up from sleep.
Bit 1 is the CRC Error Status Flag (CRC_ERROR). It is updated on every I2C write packet.
Bit 2 is the Overcurrent Alert Status Flag (ALERT). This reflects the state of the overcurrent comparator.
4.2.2
CELL_CTL: 0x01
Bits 0-2 are the cell select bits (CELL_SEL) that determine which cell voltage input (VC1
–
VC6) is sent to
the VCOUT pin.
Bits 4-5 are the VCOUT multiplexer selector bits (VCOUT_SEL). These bits determine the output of the
VCOUT pin: either VSS, VCn, Vref x 0.5, or Vref x 0.85.
4.2.3
BAL_CTL: 0x02
Bits 0-5 are for cell balance control (BAL_1
…
BAL_6).
4.2.4
CONFIG_1: 0x03
Bit 0 is the current amplifier gain select bit (I_GAIN). The gain can be set to 4 or 8.
Bit 2 is the current amplifier calibration bit (I_AMP_CAL). It is used to select the current measurement:
from SENSEN or SENSEP.
Bit 3 is the current comparator polarity select bit (I_COMP_POL). This determines the current direction
used to trip the comparator: charge or discharge.
Bits 4
–
7 determine the current comparator threshold setting (I_THRESH). Sixteen different mV levels are
available.
4.2.5
CONFIG_2: 0x04
Bit 0 is used to set the reference voltage level (REF_SEL). VREF has two different voltage levels.
Bit 7 is used to enable or disable the I2C CRC.
4.2.6
POWER_CTL: 0x05
Bit 0 is used to enable or disable the reference voltage (REF_EN).
Bit 1 is used to enable or disable the thermistors bias voltage (VTB_EN).
Bit 2 is used to enable or disable the cell voltage amplifier (VC_AMP_EN).
Bit 3 is used to enable or disable the current amplifier (I_AMP_EN).
Bit 4 is used to enable or disable the current comparator (ICOMP_EN).
Bit 6 is used to disable the sleep mode (SLEEP_DIS).
Bit 7 is used to enter sleep mode (SLEEP).
4.3
Modifying Control Registers
Control register bits that are writable can be modified by simply clicking on the bit that the user wishes to
change. The modification is immediately communicated by the Evaluation Software to the bq76925.
4.4
Sleep Mode and Wake Up
The bq76925 can be put into a low-power mode called Sleep. Bit 7 in the PWR_CTL register is called
SLEEP. When this bit is set to a 1, the part shuts down the V3P3 output and enters the low-power state.
To enter sleep mode, simply click the SLEEP bit in the Control Registers display.
19
SLUU514
–
July 2011
bq76925EVM Evaluation Module
Copyright
©
2011, Texas Instruments Incorporated