PCB Layout Guideline
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2.4.4
CHARGER CUT-OFF BY THERMISTOR (HPA207-001, -004, or -005 ONLY)
1. Slowly increase the output voltage of PS2 until Ibat = 0 ± 10mA.
Measure
→
V(J6(TS)) = 2.44V ± 400mV
2. Slowly decrease the output voltage of PS2.
Charge will resume. Continue to decrease the output voltage of PS2 slowly until Ibat = 0 ± 10mA.
Measure
→
V(J6(TS)) = 0.97V ± 400mV
3. Slowly increase the output voltage of PS2 to 1.6V ± 100mV.
Measure
→
Ibat = 3000mA ± 200mA
2.4.5
LEARN MODE (HPA207-002, -003, -006, or -007 ONLY)
1. Measure
→
V(J6(SYS)) = 19V ± 1V (adapter connected to system)
2. Uninstall JP2 (Enable the learn mode).
Measure
→
V(J6(SYS)) = 10.5V ± 1V (battery connected to system)
3. Install JP2 (Disable the learn mode).
Measure
→
V(J6(SYS)) = 19V ± 1V (adapter connected to system)
2.4.6
POWER PATH SELECTION
1. Install JP9 (Disable the charging).
Measure
→
V(J6(SYS)) = 19V ± 1V (adapter connected to system)
Observe
→
D4 (ACDRV) on, D6 (BATDRV) off.
2. Turn off PS1.
Measure
→
V(J6(SYS)) = 10.5V ± 1V (battery connected to system)
3
PCB Layout Guideline
1. It is critical that the exposed power pad on the backside of the bq2475x package be soldered to the
PCB ground. Make sure there are sufficient thermal vias right underneath the IC, connecting to the
ground plane on the other layers.
2. The control stage and the power stage should be routed separately. At each layer, the signal ground
and the power ground are connected only at the power pad.
3. AC current sense resistor must be connected to ACP (pin 3) and ACN (pin 2) with a Kelvin contact.
The area of this loop must be minimized. The decoupling capacitors for these pins should be placed as
close to the IC as possible.
4. Charge current sense resistor must be connected to SRP (pin 19), SRN (pin 18) with a Kelvin contact.
The area of this loop must be minimized. The decoupling capacitors for these pins should be placed as
close to the IC as possible.
5. Decoupling capacitors for PVCC (pin 28), VREF (pin 10), REGN (pin 24) should be placed underneath
the IC (on the bottom layer) and make the interconnections to the IC as short as possible.
6. Decoupling capacitors for BAT (pin 17), IADAPT or IBAT (pin 15) must be placed close to the
corresponding IC pins and make the interconnections to the IC as short as possible.
7. Decoupling capacitor(s) for the charger input must be placed close to Q3 drain and Q4 source.
8
bq24750/50A/51/51A/51B/52/53 EVM (HPA207) For Multi —Cell Synchronous
SLUU283D – May 2007 – Revised March 2010
Notebook Charger and System Power Selector
Copyright © 2007–2010, Texas Instruments Incorporated