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PCB Layout Guideline
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PCB Layout Guideline
1. It is critical that the exposed thermal pad on the backside of the bq24650 package be soldered to the
PCB ground. Ensure that sufficient thermal vias are right underneath the IC, connecting to the ground
plane on the other layers.
2. The control stage and the power stage must be routed separately. At each layer, the signal ground and
the power ground are connected only at the thermal pad.
3. Charge current sense resistor must be connected to SRP, SRN with a Kelvin contact. The area of this
loop must be minimized. The decoupling capacitors for these pins must be placed as close to the IC as
possible.
4. Decoupling capacitors for VREF, VCC, REGN must make the interconnections to the IC as short as
possible.
5. Decoupling capacitors for BAT must be placed close to the corresponding IC pins, and make the
interconnections to the IC as short as possible.
6. Decoupling capacitor(s) for the charger input must be placed close to the Q1A drain and Q1B source.
7. Take the EVM layout for design reference.
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SLUU444A – August 2010 – Revised October 2010
bq24650EVM Synchronous, Switch-Mode, Battery Charge Controller for Solar
Power
Copyright © 2010, Texas Instruments Incorporated