i.MX 6Solo, 6DualLite
Processor
VDD_ARM, VDD_SOC
(LDO_PU, LDO_SoC, LDO_ARM enabled)
VDD_HIGH_IN
(LDO_2P5, LDO_1P1, LDO_SNVS enabled)
VDD_SNVS_IN
NVCC_GPIO, NVCC_SD1-3,
NVCC_ENET, NVCC_CSI,
NVCC_EIM, NVCC_LCD,
NVCC_NANDF, NVCC_JTAG
DRAM_VREF
DRAM Memory Module
VDD, VDDQ, VDDCA,
VDD1, VDD2
VREF
R
REF
R
REF
TPS652170
PMIC
DCDC1
DCDC2
LDO1
LDO2
3.0 V
2.5 V
1.2 A
1.2 A
3.0 V
1.425 V
1.35 V
100 mA
2.5 V
Peripheral
VIN (5 V)
100 mA
from internal
LDOs
HDMI_VP, PCIE_VP, PCIE_VPTX
from internal
LDOs
NVCC_LVDS2P5,
HDMI_VPH, PCIE_VPH, NVCC_MIPI
Copyright © 2018, Texas Instruments Incorporated
NVCC_DRAM,
NVCC_DRAM_CKE
DCDC3
1.2 A
LS1 (LDO3)
3.3 V
400 mA
3.3 V
Peripheral
LS2
USB_HI_VBUS, USB_OTG_VBUS
200 mA
3
2
3
1
4
Re-Programming the EEPROM of the TPS652170 Device
18
SLVUBH6 – November 2018
Copyright © 2018, Texas Instruments Incorporated
Software Instructions
(1)
The power-on sequence order is listed for each rail, numbered 1-4.
Figure 17. TPS652170 Re-Programming Example Block Diagram
•
The voltage setpoint of DCDC1 has already been modified, so only the remaining DC/DC converters
and LDO1 regulator voltages need to be modified at this time.
shows the new output voltage
setpoint configured in the
DEFDCDC2
,
DEFDCDC3
,
DEFLDO1
,
DEFLDO1
,
DEFLS1
, and
DEFLS2
registers (0x0F, 0x10, 0x12, 0x13, 0x14, and 0x15) as well as the correct
PASSWORD
register (0x10)
value written automatically by the IPG-UI.