00
01
10
11
Divider
TA0CLK
ACLK
SMCLK
Input
Logic
Input
Logic
00
01
10
11
DVSS
DVCC
00
01
10
11
P1.1
from RTC
DVSS
DVCC
Output
Logic
Output
Logic
P1.1
TA0CCTL1.CCIS
TA0CTL.TASSEL
TA0CCTL2.CCIS
P1.2
00
01
10
11
Divider
TA1CLK
ACLK
SMCLK
Input
Logic
Input
Logic
00
01
10
11
P1.4
DVSS
DVCC
00
01
10
11
P1.5
DVSS
DVCC
Output
Logic
Output
Logic
P1.5
TA1CCTL1.CCIS
TA1CTL.TASSEL
TA1CCTL2.CCIS
P1.4
from CapTouchIO
(INCLK)
to ADC Trigger
Timer0_A3
Timer1_A3
Comparator 1
CCR2
Comparator 2
CCR1
Comparator 0
Counter
CCR0
Comparator 1
CCR2
Comparator 2
CCR1
Comparator 0
Counter
CCR0
0
1
0
1
From UCA1TXD/UCA1SIMO
SYSCFG1.IRDATA
SYSCFG1.IRDSSEL
SYSCFG1.IRPSEL
P2.6/UCA1TXD/UCA1SIMO
SYSCFG1.IRMSEL
1
0
0
1
1
0
SYSCFG1.IREN
0
1
IR Modulation (SYS)
from CapTouchIO
(TA0.1B)
(TA0.2B)
(TA1.2B)
(TA1.1B)
(TA1.2B)
(TA0.1A)
(TA0.1B)
(TA0.2A)
(TA0.2B)
(TA0.1A)
(TA0.2A)
(TA1.2A)
(TA1.1A)
(TA1.1B)
(TA1.1A)
(TA1.2A)
Output
Logic
(TA0.0B)
(TA0.0A)
Input
Logic
00
01
10
11
DVSS
DVCC
TA0CCTL0.CCIS
(TA0.0A)
(TA0.0B)
Input
Logic
00
01
10
11
DVSS
DVCC
TA1CCTL0.CCIS
(TA1.0B)
(TA1.0A)
Output
Logic
(TA1.0B)
(TA1.0A)
P1.2
INCLK
TI Design and Software Examples
Figure 8. IR Modulation Logic Blocks in MSP430FR4133
shows the ASK IR Modulation signal generation used in the example software for this TI Design,
found in the
MSP-EXP430FR4133 Software Examples
. TA0CCR2 output is used as the carrier frequency,
and is ANDed with TA1CCR2 which is generating the envelope, before the final resulting signal is brought
out on the output pin.
Therefore to generate the signal, TA0CCR0 and TA0CCR2 are set once at the beginning of the code to
generate a 38-kHz PWM for the carrier signal. For each bit to be sent, the TA1CCR0 and TA1CCR2
values are updated to generate a PWM with the correct envelope timing for sending a 0 or 1 using Pulse
Distance Encoding.
12
BOOST-IR Infrared (IR) BoosterPack™ Plug-in Module
SLAU598A – December 2014 – Revised July 2015
Copyright © 2014–2015, Texas Instruments Incorporated
