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3.4.9.1 DP83867 PHY Default Configuration
The DP83867 PHY uses four level configurations based on resistor strapping, which generates four distinct
voltages ranges. The resistors are connected to the RX data and control pins that are normally driven by the
PHY and are inputs to the AM64x. The voltage range for each mode is shown below:
Mode 1 - 0 V to 0.3234 V
Mode 2 – 0.462 V to 0.6303 V
Mode 3 – 0.7425 V to 0.9372 V
Mode 4 – 2.2902 V to 2.904 V
DP83867 device includes internal pull-down resistor. The value of the external pull resistors is selected to
provide voltage at the pins of the AM64x as close to ground or 3.3V as possible. The strapping is shown in
Figure 3-21 and strap values shown in Table 3-19 .
Address strapping is provided for CPSW PHY to set address -00000 (0h) by default, as strapping pins has
internal pull-down resistors. Footprint for both pull up and pull down is provided on all the strapping pins except
LED_0. LED_0 is for Mirror Enable, which is set to mode 1 by default, Mode 4 is not applicable and Mode2,
Mode3 option is not desired.
3.4.9.2 DP83869 PHY Default Configuration
The DP83869 PHY uses four level configurations for I/O, RX_D0 and RX_D1 pins and two-level configurations
for all other pins. The four level strap pins based on resistor strapping generates four distinct voltages ranges.
The resistors are connected to the RX data pins, which are normally driven by the PHY and are inputs to the
AM64x. The voltage range for each mode is shown below:
Mode 0 - 0 V to 0.3069 V
Mode 1 – 0.4488 V to 0.6072 V
Mode 2 – 0.7227 V to 0.924 V
Mode 3 – 1.98 V to 2.9304 V
The two level strap pins based on resistor strapping generates two distinct voltage ranges. The resistors are
connected to the LED pins. Because the LED output pins are also used as straps, the external components
required for strapping and LED usage must be considered to avoid contention. Specifically, this may be an issue
when the LED outputs are used to drive LED directly. The voltage range for each mode is shown below:
Mode 0 - 0 V to 0.594 V
Mode 1 – 1.65 V to 2.904 V
DP83869 device includes internal pull-down resistor. The value of the external pull resistors is selected to
provide voltage at the pins of the AM64x as close to ground or 3.3 V as possible. The strapping is shown in
Figure 3-21 and the strap values are given in Table 3-20 .
Address strapping is provided for ICSSG1 PHY to set address of 00011 (03h) and ICSSG2 PHY to set address
of 01111 (0Fh) using the strap resistors. Footprint for both pull up and pull down is provided on all the strapping
pins.
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SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021
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