3.4 Peripheral and Major Component Description
The following sections provide an overview of the different interfaces and circuits on the AM64x/AM243x EVM.
3.4.1 Clocking
3.4.1.1 Ethernet PHY Clock
A clock generator of part number
CDCLVC1310
is used to drive 25 MHz clock to the Ethernet PHYs.
CDCLVC1310 is a 1:10 LVCMOS clock buffer, which takes 25 MHz crystal/LVCMOS reference input and
provides ten 25 MHz LVCMOS clock outputs. The source for the clock buffer is either the CLKOUT0 pin from
the SoC or a 25 MHz oscillator
(ASFLMB-25.000MHZ-LY-T)
, the selection is made using a set of resistors. This
selection can be made through the select lines of the clock buffer.
1.
IN_SEL0, IN_SEL1 = [00]
for selecting CLKOUT0.
2.
IN_SEL0, IN_SEL1 = [01]
for selecting oscillator input. This is the default condition.
The resistor termination for single ended Crystal input is provided as per device-specific data sheet.
Table 3-1. Source Clock Selection for the Clock Buffer
IN_SEL1
IN_SEL0
Clock Chosen
Mount
Unmount
0
0
EXT_REFCLK from SoC
R40, R45
R248, R253
1
0
Oscillator input
R253, R40
R45, R248
Figure 3-4. AM64x/AM243x EVM Clock Tree
Note
Resistors that are marked with red color box are DNI.
3.4.1.2 AM64x/AM243x Clock
Crystal of 25 MHz
(ABM10W-25.0000MHZ-8-K1Z-T3)
is provided on EVM as reference clock for the AM64x/
AM243x device. An optional output from the buffer driving the AM64x/AM243x is provided. Selection of clock for
SoC is done using resistors. By default, an output from clock buffer SoC_CLKIN is provided to SoC.
3.4.1.3 PCIe Clock
The PCIe reference clock to the SoC will be provided by the PCIe slot connector when processor is configured
as downstream port and PCIe reference clock from the SoC (SERDES0_REFCLK0) will be provided to the PCIe
slot connector during root complex mode of operation.
System Description
SPRUJ63 – SEPTEMBER 2022
AM64x/AM243x EVM User's Guide
11
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