Dynamic Voltage and Frequency Scaling (DVFS)
9.8.1 Frequency Scaling Considerations
The operating frequency of the device is controlled through its two PLL controllers (PLLC0 and PLLC1).
Through a series of multipliers and dividers you can change the frequencies of various clocks throughout
the device. See
for information on the clock architecture of the device and see
for
information on the PLL controllers. A few things must be noted when changing the various internal
frequencies of the device:
•
Changing the SYSCLK frequency
The PLL_VCO (PLLOUT) frequency can be programmed through a PLL multiplier. A series of dividers
divide PLLOUT to generate the various device SYSCLKs.
To change the SYSCLK frequency you can change the PLL multiplier or you can change the SYSCLK
divider ratio. When changing the PLL multiplier, you must put the PLL controller in bypass mode while
the PLL multiplier value is modified and a lock on the new frequency is reached. The lock time is given
in the device data manual. When changing the divider ratios it is not required to put the PLL controller
in bypass mode.
Changing the SYSCLK frequency through the dividers is faster as there is no need to reprogram the
PLL. However, the SYSCLK frequency will depend solely on the divider ratios used.
•
SYSCLK domain fixed ratios
Certain SYSCLK domains need to operate at a fixed ratio with respect to the ARM clock. Care should
be taken to ensure that these fixed ratios are maintained. For additional details, see
.
•
PLLC0 bypass clock
When switching the PLL multiplier, the PLL controller must be placed in bypass mode. Bypassing the
PLL sends a bypass clock instead of the PLL VCO output (PLLOUT) to the system clock dividers of
the PLL controller.
For PLLC0 the bypass clock is selected from either the PLL reference clock (OSCIN) or
PLL1_SYSCLK3. For PLLC1, the bypass clock is always OSCIN. The OSCIN frequency is typically, at
most, up to 50 MHZ.
You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low
maintenance levels without using the PLL during periods of very low system activity.
It may be desirable for the bypass clock to not revert to OSCIN in some situations to preserved
bandwidth during frequency scaling transitions. For this reason, the PLLC0 bypass clock can be set to
PLL1_SYSCLK3. This selection is made through the EXTCLKSRC bit in the PLLCTL register of
PLLC0.
•
Peripheral immunity from ARM clock frequency changes
Peripherals that are clocked by the PLL0_AUXCLK are immune to changes in the PLL0 frequency.
The PLL0_AUXCLK is derived from OSCIN.
Peripherals in the ASYNC3 domain are clocked off from either PLL1_SYSCLK2 or PLL0_SYSCLK2.
Furthermore, PLL0_SYSCLK2 must always be /2 of the ARM clock frequency. To keep these
peripherals immune from changes in PLL0 frequency (such as when the ARM frequency is modified),
you can configure the ASYNC3 domain to be clocked from PLL1_SYSCLK2. PLL1 is mainly used to
clock the DDR2/mDDR memory controller.
When peripherals are immune to changes in the ARM clock frequency, their internal clock dividers do
not have to be adjusted for changes in their input clock frequencies.
9.8.2 Voltage Scaling Considerations
The operating voltage of the device must be totally controlled through mechanisms outside the device. I2C
ports on the device can be used to communicate with external power management chips. A few things
must be noted when changing the operating voltage of the device:
•
Voltage ramp rate: The ramp rate of the operating voltage must be observed during operating
performance point (OPP) transitions. See the device data manual for ramp rate specifications.
•
Switching to a lower voltage: When switching to a lower voltage, the maximum operating frequency
changes. Care must be taken such that the maximum operating frequency supported at the new
voltage is not violated. For this reason, it is recommended to change the operating frequency before
switching the operating voltage.
138
Power Management
SPRUGX5A
–
May 2011
Copyright
©
2011, Texas Instruments Incorporated
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