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Board Operation
When HP8644 or similar clock sources are not available, the on-board 40MHz clock is also a desirable
source. The jumpers P4, 5, 6 should be configured as
shows (i.e., default setup for
AFE5801EVM). In this mode, the transform-based differential clock is used.
3.6
Data Analysis
Based on the data file acquired by a logic analyzer, the performance of AFE5801 can be evaluated.
In Appendix A, we provide one solution (TI TSW1250 EVM) to analyze the data file using the PC.
Appendix B provides an alternate solution (TI TSW1100 software) to analyze the data file captured by a
logic analyzer. Coherent sampling is recommended if the input and sampling clock are phase locked. Due
to the frequency accuracy requirement of coherence sampling, two HP8644s for generating ADC clock
and analog signal are required. For most users, this may not be feasible. Data analysis based on
windowing is a more suitable approach.
15
SLOU257A
–
October 2009
–
Revised July 2011
AFE5801 8-Channel Variable Gain Amplifier (VGA) with Octal High-Speed ADC
Copyright
©
2009
–
2011, Texas Instruments Incorporated