17
ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955
ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961
SLAS605C – JUNE 2008 – REVISED JULY 2018
Product Folder Links:
ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958
Copyright © 2008–2018, Texas Instruments Incorporated
(1)
1.8V specifications apply from 1.7 V to 1.9 V, 3 V specifications apply from 2.7 V to 3.6 V, 5 V specifications apply from 4.75 V to
5.25 V.
(2)
With 50-pF load
7.9 Timing Requirements
All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified)
(1) (2)
(see
,
, and
MIN
NOM
MAX
UNIT
t
conv
Conversion time
+VBD = 1.8 V
16
SCLK
+VBD = 3 V
16
+VBD = 5 V
16
t
q
Minimum quiet sampling time needed from bus 3-
state to start of next conversion
+VBD = 1.8 V
40
ns
+VBD = 3 V
40
+VBD = 5 V
40
t
d1
Delay time, CS low to first data (DO–15) out
+VBD = 1.8 V
38
ns
+VBD = 3 V
27
+VBD = 5 V
17
t
su1
Setup time, CS low to first rising edge of SCLK
+VBD = 1.8 V
8
ns
+VBD = 3 V
6
+VBD = 5 V
4
t
d2
Delay time, SCLK falling to SDO next data bit valid
+VBD = 1.8 V
35
ns
+VBD = 3 V
27
+VBD = 5 V
17
t
h1
Hold time, SCLK falling to SDO data bit valid
+VBD = 1.8 V
7
ns
+VBD = 3 V
5
+VBD = 5 V
3
t
d3
Delay time, 16
th
SCLK falling edge to SDO 3-state
+VBD = 1.8 V
26
ns
+VBD = 3 V
22
+VBD = 5 V
13
t
su2
Setup time, SDI valid to rising edge of SCLK
+VBD = 1.8 V
2
ns
+VBD = 3 V
3
+VBD = 5 V
4
t
h2
Hold time, rising edge of SCLK to SDI valid
+VBD = 1.8 V
12
ns
+VBD = 3 V
10
+VBD = 5 V
6
t
w1
Pulse duration CS high
+VBD = 1.8 V
20
ns
+VBD = 3 V
20
+VBD = 5 V
20
t
d4
Delay time CS high to SDO 3-state
+VBD = 1.8 V
24
ns
+VBD = 3 V
21
+VBD = 5 V
12
t
wh
Pulse duration SCLK high
+VBD = 1.8 V
20
ns
+VBD = 3 V
20
+VBD = 5 V
20
t
wl
Pulse duration SCLK low
+VBD = 1.8 V
20
ns
+VBD = 3 V
20
+VBD = 5 V
20
Frequency SCLK
+VBD = 1.8 V
20
MHz
+VBD = 3 V
20
+VBD = 5 V
20
