Texas Instruments ADS62PXXEVM, Руководство пользователя

Страница: 21 / 27

www.ti.com
Connecting to FPGA Platforms
4.1.2 Test Result With Onboard VCXO and Clock Through Crystal Filter
This test uses the VCXO of frequency 983.04 MHz. This setup uses the Power Option 1 ( Table 3 ), Analog
Input Option 1 ( Table 5 ), and Clock Option 2 ( Table 7 ). For this test, the CDCE72010 crystal filter path
was chosen to provide the clock to the ADC. The CDCE72010 provides a single-ended clock through
output Y0 (
Table 7 ), which is passed through a crystal filter of center frequency 245.76 MHz. This was the
example setup; the VCXO and the crystal filter are not populated on the EVM because the values depend
on the end application sampling rate. The capture result for ADS62PXX is as shown in
Figure 10 .
Figure 10. ADC Performance With Clock Through Onboard VCXO, CDCE72010 and Crystal Filter
21 SLAU237B – May 2008 – Revised July 2010 ADS62PXXEVM
Copyright © 2008–2010, Texas Instruments Incorporated