Texas Instruments ADS62PXXEVM, Руководство пользователя

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Circuit Description
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Figure 3. CDCE72010 EEPROM Configuration Block Diagram
2.2.4.3 Clock Option 3
Option 3 is used for a differential LVPECL clock. This configuration eliminates the need for a crystal filter.
It uses the same EEPROM configuration as Option 2, but in this case, the ADC clock pins are connected
to Y1N and Y1P. The jumper setting uses the clock output Y1P and Y1N from CDCE72010, to clock ADC.
This configuration is not recommended for SNR critical applications. Notice that the clock frequency does
not change. The frequency remains the same as in Clock Option 2. The test result using this option is
shown in
Figure 11 .
2.2.5 ADC Digital Outputs
The LVDS digital outputs can be accessed through the J8 output connector. A parallel 100- Ω termination
resistor must be placed at the receiver to properly terminate each LVDS data pair. These resistors are
required if the user wants to analyze the signals on an oscilloscope or a logic analyzer. The ADC
performance also can be quickly evaluated using the TSW1200 boards as explained in the next section.
The TSW1200 will automatically terminate the LVDS outputs once the TSW1200 is connected to J8.
The ADS62PXX and most other ADCs that may be evaluated on this EVM also have an option to output
the digitized parallel data in the form of single-ended CMOS. If single-ended CMOS is desired, header
post connectors J1 and J2 are provided for the CMOS output. In order to use the header J1, a CMOS
buffer U12 must be installed in place of a bank of 0-ohm resistors that by default steer the outputs to the
LVDS connector J8. And in order to use the header J2, a CMOS buffer U13 must be installed in place of a
bank of 0-ohm resistors that by default steer the outputs to the LVDS connector J8.
2.2.6 LEDs on the EVM
There are four LEDs on the EVM. LED D4 is named as ADC VD; this LED illuminates when the 3.3V
digital supply is available to the ADC by setting jumper JP18 to position 1-2. Similarly, LED D5 (ADC VA)
illuminates when the 3.3V analog supply is available to the ADC by setting jumper JP15 to position 1-2.
LED D6 is 3.3V AUX, which illuminates when the 3.3V auxiliary supply is available from TPS79633. LED
D3 is the PLL LOCK LED. This LED illuminates when the CDCE72010 PLL is locked.
14 ADS62PXXEVM SLAU237B – May 2008 – Revised July 2010
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