2
Circuit and Operational Description
2.1
Schematic Diagram
2.2
Power
2.3
Clock Input
2.4
Analog Input
Circuit and Operational Description
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Figure 1. Board Layout
Power is supplied via the 6-Vdc external power supply which is then distributed onboard using several
voltage regulators.
A single-ended sinusoidal clock with a 50% (
±
3%) duty cycle must be applied to the SMA clock input, J10.
The output swing of the clock must be
±
1 V. The clock frequency must not exceed 400 MSPS for the
ADS5474. The single-ended clock input is converted into a differential signal by using a transformer. The
0
°
phase output of the transformer is used to clock ADC1 whereas the 180
°
phase output is used to clock
ADC2.
A single-ended analog input must be applied to the SMA analog input, J9. The amplitude of the signal
must not exceed 2.2-Vpp differential at the input of the ADCs. The analog input is converted into a
differential signal by using a transformer and is fed to both ADCs. When providing an analog input,
consider the following guidelines for correct operation of the ADX IP core when enabled.
1. The analog input must be less the 85% of the Nyquist band. The Nyquist band refers to one-half of the
combined interleaved sampling rate of the analog input signal.
2. On initial power up, the analog input must be greater than 7.5% of the Nyquist band for correct
estimation to occur. After estimation has occurred, one can put analog input signals representing less
then 7.5% of the Nyquist band.
3. For single- tone analysis only, users cannot input a tone of FS/4 and have adequate correction of the
interleaved tone. In this case, the interleaved spur falls on top of the wanted single tone, which cannot
be distinguished by the ADX algorithm. FS refers to the combined sampling rate of the analog input.
ADS5474 ADX Evaluation Board for Interleaving
4
SLAU247 – August 2008
