14.3 Schematic
Printed-Circuit Board Layout, Bill of Materials, and Schematic
www.ti.com
Figure 14. Front End Schematic
22
ADS5474 ADX Evaluation Board for Interleaving
SLAU247 – August 2008
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Страница 1: ...ture Single Batch 10 5 4 Continuous Capture 10 6 Import and Export of Data 10 6 1 Import Data 10 6 2 Export Data 10 7 Data Analysis 10 7 1 Analysis Settings 10 7 2 Analysis Window Output 11 8 Plot Tools 12 9 Keyboard Commands 12 10 MATLAB Interface 13 11 Results 13 12 Troubleshooting 15 13 SP Devices Intellectual Property 15 14 Printed Circuit Board Layout Bill of Materials and Schematic 16 14 1 P...
Страница 2: ... 16 USB and Logic Analyzer Connectors 24 17 FPGA System Schematic 25 18 Power Supply Schematic 26 List of Tables 1 DIP Switches Functional Descriptions 5 2 DIP Switches Modes 5 3 LED Functions 5 4 Bill of Materials 20 MATLAB is a trademark of The MathWorks Inc ADS5474 ADX Evaluation Board for Interleaving 2 SLAU247 August 2008 Submit Documentation Feedback ...
Страница 3: ...be clocked with a 50 duty cycle clock at half of the sampling rate of the interleaved system sampling rate The interleaving and digital post correction ADX IP core is implemented in real time using the Virtex 5 FPGA on the board Digital output from the EVM is provided both by two Soft Touch Probe support for Agilent E5405A and Tektronix P6908 probes connectors for logic analyzers and by a USB conn...
Страница 4: ... the input of the ADCs The analog input is converted into a differential signal by using a transformer and is fed to both ADCs When providing an analog input consider the following guidelines for correct operation of the ADX IP core when enabled 1 The analog input must be less the 85 of the Nyquist band The Nyquist band refers to one half of the combined interleaved sampling rate of the analog inp...
Страница 5: ... data The signal is reconstructed for the second Nyquist band Four LEDs are on the board A more thorough description on the signal requirements for estimation is available in the data sheet for the ADX IP core Table 3 LED Functions LED Color Description D4 Green On Channel mismatch has been estimated and outputs are valid to specification Off Channel mismatch is not estimated output may be outside...
Страница 6: ... DIP switches The onboard USB1 1 chip communicates with the FPGA Transfer speed is 3 megabaud To install the software run the ADCaptureLab setup exe file and follow the instructions for installation Before continuing you need to close any other application running to avoid the need of rebooting the system 6 ADS5474 ADX Evaluation Board for Interleaving SLAU247 August 2008 Submit Documentation Feed...
Страница 7: ...om the installation program the drivers are pre installed on your hard disk but are not activated until you connect a powered ADS ADX EVM to the computer for the first time SLAU247 August 2008 ADS5474 ADX Evaluation Board for Interleaving 7 Submit Documentation Feedback ...
Страница 8: ...FT plot Plot tools 8 SETTINGS SETUP 5 1 Connect Capture 5 2 Import Export Plot settings 7 1 Time series plot of data View www ti com ADS5474 ADX Evaluation Board for Interleaving 8 SLAU247 August 2008 Submit Documentation Feedback ...
Страница 9: ...oard Available choices 1 ADX EVM 2xADS5463 12b 2 ADX EVM 2xADS5474 14b 1 To find a board push the button labeled Find USB Devices The boards connected to the computer then show up in the Devices box Status information on the enumeration of devices shows in Log window 2 Select a compatible device board from the Devices list The buttons Acquire data and Run are then activated SLAU247 August 2008 ADS...
Страница 10: ...e capturing If plots are in Play mode see Section 7 plots are updated continuously as new data arrives from the board Select a file file on text file format supported in dialog box and press Open File contents are loaded into the plot windows unless they are in Pause mode To import you can also drag and drop the file to the ADCaptureLab main window directly Select filename in dialog box and press ...
Страница 11: ...s the color scheme of the plot routines Available modes are White background printer friendly Black background Window Windowing function used for FFT and for analysis functions Available Blackman Hamming Rectangular Autoscale FFT Y Axis When enabled autoscales the y axis of the FFT plot If disabled y axis is locked between 0 and 130 dBFS Mark signal props When enabled fundamental tone s and SFDR l...
Страница 12: ...nd distortion ENOB Single tone Effective Number Of Bits Based directly on the SNDR value Two tone If the mouse cursor is placed in the upper right side of any of the plot windows a plot toolbar shows Plot tool Description Play Pause To put plot in Play Pause mode In play mode plot displays new data as it arrives either by acquiring or by importing from file In pause mode plot does not update Copy ...
Страница 13: ...ire The following typical results were taken from the ADS ADX evaluation module using a filtered Agilent 8644B clock source which provided each ADC a 400 MHz sampling clock When using the onboard ADX interleaving technology this results in a combined 800 MSPS sampling rate of the analog input signal Another filtered Agilent 8644B was used to provide a 1 dBFS single tone into the EVM The results ar...
Страница 14: ...0 100 120 50 60 70 80 90 100130 170230 250 270 491 650 f Frequency Hz Offset SFDR dBc Image Results www ti com Figure 4 491 5 MHz Figure 5 ADS5474 ADX ADS5474 ADX Evaluation Board for Interleaving 14 SLAU247 August 2008 Submit Documentation Feedback ...
Страница 15: ... and found in list but when trying to Check if board is powered acquire board does not respond correctly Check that correct board format is selected in Setup Settings 5 1 Try to push the onboard reset button Press Find USB Devices again select board and retry Try to turn the power off and on again Press Find USB Devices again select board and retry Time series plot or FFT does not update when acqu...
Страница 16: ...uit Board Layout Printed Circuit Board Layout Bill of Materials and Schematic www ti com The following illustrations show the eight layers of the ADX evaluation board Figure 6 Layer 1 16 ADS5474 ADX Evaluation Board for Interleaving SLAU247 August 2008 Submit Documentation Feedback ...
Страница 17: ...ww ti com Printed Circuit Board Layout Bill of Materials and Schematic Figure 7 Layer 2 Figure 8 Layer 3 SLAU247 August 2008 ADS5474 ADX Evaluation Board for Interleaving 17 Submit Documentation Feedback ...
Страница 18: ...inted Circuit Board Layout Bill of Materials and Schematic www ti com Figure 9 Layer 4 Figure 10 Layer 5 18 ADS5474 ADX Evaluation Board for Interleaving SLAU247 August 2008 Submit Documentation Feedback ...
Страница 19: ...w ti com Printed Circuit Board Layout Bill of Materials and Schematic Figure 11 Layer 6 Figure 12 Layer 7 SLAU247 August 2008 ADS5474 ADX Evaluation Board for Interleaving 19 Submit Documentation Feedback ...
Страница 20: ... R37 R39 R40 R65 R121 R122 R124 R125 1 100 000 097 Resistor 10 kΩ 0402 1 0 063W 0402 R43 0 100 001 043 Resistor 56 Ω 0603 1 0 1W 0603 4 100 001 047 Resistor 82 Ω 0603 1 0 1W 0603 R30 R33 1 100 001 069 Resistor 680 Ω 0603 1 0 1W 0603 R100 1 100 001 083 Resistor 2 7 kΩ 0603 1 0 1W 0603 R28 1 100 001 091 Resistor 5 6 kΩ 0603 1 0 1W 0603 R41 1 100 001 093 Resistor 6 8 kΩ 0603 1 0 1W 0603 R69 1 100 001...
Страница 21: ...5DB321D SU U5 1 103 005 002 DS2432 1 kbit protected 1 wire EEPROM with SHA 1 TSOC8 Maxim DS2432 U20 engine 2 103 010 014 PTH08080W 2 2A DC DC module 4 5 18V in 0 9 5 5V out SMD Texas Instruments PTH08080WAZ U10 U11 1 103 010 016 REG104GA 3 3G4 3 3V LDO 1A max 480mV drop SOT223 6 Texas Instruments REG104GA 3 3 U9 1 103 010 017 REG104FA 5 5V LDO 1A max 580mV drop DDPAK 5 Texas Instruments REG104FA 5...
Страница 22: ...hematic Printed Circuit Board Layout Bill of Materials and Schematic www ti com Figure 14 Front End Schematic 22 ADS5474 ADX Evaluation Board for Interleaving SLAU247 August 2008 Submit Documentation Feedback ...
Страница 23: ...www ti com Printed Circuit Board Layout Bill of Materials and Schematic Figure 15 FPGA I O Schematic SLAU247 August 2008 ADS5474 ADX Evaluation Board for Interleaving 23 Submit Documentation Feedback ...
Страница 24: ...d Circuit Board Layout Bill of Materials and Schematic www ti com Figure 16 USB and Logic Analyzer Connectors 24 ADS5474 ADX Evaluation Board for Interleaving SLAU247 August 2008 Submit Documentation Feedback ...
Страница 25: ...www ti com Printed Circuit Board Layout Bill of Materials and Schematic Figure 17 FPGA System Schematic SLAU247 August 2008 ADS5474 ADX Evaluation Board for Interleaving 25 Submit Documentation Feedback ...
Страница 26: ...rinted Circuit Board Layout Bill of Materials and Schematic www ti com Figure 18 Power Supply Schematic 26 ADS5474 ADX Evaluation Board for Interleaving SLAU247 August 2008 Submit Documentation Feedback ...
Страница 27: ...uct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI products or...
Страница 28: ...usiness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all neces...
