ADS1278EVM-CVAL Hardware Details
17
SBAU324 – September 2018
Copyright © 2018, Texas Instruments Incorporated
ADS1278EVM-CVAL Evaluation Module User's Guide
Table 6. Jumper and Switch Descriptions (continued)
Jumper/Switch
Functions
Descriptions
(2)
Refer to
for more details.
S6
Serial Interface format
FS - Frame Sync format. [1-2], [4-5], [7-8], [10-11] installed.
(2)
SPI - SPI-compatible mode. [2-3], [5-6], [8-9], [11-12] installed.
(2)
S7
Channel 2 input source selector
Selects Channel 2 input source - header or input buffer
Left - header
Right - input buffer
S8
Channel 1 input source selector
Selects Channel 1 input source - header or input buffer
Left - header
Right - input buffer
5.2
Power-Down, MODE, and FORMAT Control
The ADS1278-SP has several pins to control the power-down of individual channels and select the mode
and format for the digital interface.
For users of the ADS1278EVM-CVAL as a stand-alone module, these pins may be pulled high or low
through DIP switches
S1
and
S2
(see
). Refer to the
for complete
details on these pins and which state sets which options.
For use with the MMB0 motherboard, the state of these pins is controlled by software, using the I
2
C port
expanders (U7 and U8) on the EVM. With this configuration, the DIP switches
S1
and
S2
must all be
switched up (away from the center of the board). The ADS1278EVM-CVAL software checks at startup to
verify that these switches are set correctly, and generates an error message for incorrect settings. The
software cannot detect if the switches are changed after startup.
CAUTION
When using the ADS1278EVM-CVAL with the MMB0 motherboard, the DIP
switches
S1
and
S2
must all be switched up (away from the center of the
board). Failure to do so may damage the EVM.
5.3
Clock Source
The ADS1278-SP clock can come from one of several sources: the onboard 27-MHz crystal oscillator, a
clock supplied by a processor on the TOUT pin (
J4.17
), or an external clock source connected between
J4.17
(TOUT) and
J4.18
(DGND).
If the onboard 27-MHz oscillator is selected, the device can be run in high-speed mode, high-resolution
mode, low-power mode, or low-speed modes with
CLKDIV
set to 1.
If the performance of the device must be explored with
CLKDIV
set to 0 in the low-power and low-speed
modes, an external clock must be provided to the board, either using the TOUT connection or having an
external clock source connected to
J4.17
. The same condition is true if frequencies other than the 27 MHz
provided by the onboard oscillator must be investigated.
5.4
Analog Headers, J1 and J3
For maximum flexibility, the ADS1278EVM-CVAL is designed for easy interfacing to multiple analog
sources. These headers/socket provide access to the analog input pins of the ADS1278-SP.
Four of the analog input sources (Channels 1–4) connect directly to
J3
(top or bottom side) or through
signal-conditioning modules available for the modular EVM system. These inputs have provisions to buffer
the inputs using THS4521 before connecting to the converter. Switches
S4, S5, S7
, and
S8
provide the
capability to connect either the header directly or through a buffer. When the buffers are not selected, the
op-amps used for buffering can be powered down by shorting
JP3
.