Texas Instruments ADC368 EVM Series Скачать руководство пользователя страница 27 | Manualshive

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Texas Instruments ADC368 EVM Series Скачать руководство пользователя страница 27

8 Test Pattern

It is often useful to utilize test patterns to help verify the correct reciept of digital data at the microcontroller or
FPGA. A ramp pattern can be enabled by following these steps:
• Click the yellow button "Analog Inputs and Clk"
• Next to "Test Pattern CHA", click the drop down menu, and select "RAMP CUSTOM". This can be done for

"Test Pattern CHB" as well.

• In the field next to "Custom Pattern",

– For 18 bit ramp mode (ADC3683EVM, ADC3682EVM), "1" must be entered in the "Custom Pattern" field.

• The digital ramp pattern is now enabled on the ADC. The output of the ADC is now an 18 bit, incrementing

ramp pattern.

Figure 8-1. ADC36xxEVM 18-bit Ramp Pattern

• In HSDC Pro, the ramp pattern can now be seen when data is captured. These same steps apply to any data

output mode (Bypass, Real Decimation and Complex Decimation).
– It may be necessary to increase the capture sample size to 524k to capture the entire ramp pattern in 18

bit mode.

– In HSDC Pro, click "Data Capture Options" -> "Capture Option", and enter "524288" in the "# of samples

(per channel)" field.

Test Pattern

SBAU360 – DECEMBER 2020

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ADC368xEVM Evaluation Module

27

Copyright © 2020 Texas Instruments Incorporated

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Содержание ADC368 EVM Series

Страница 1: ...Abstract 1 1 Introduction 2 2 Equipment 2 2 1 ADC368xEVM Functionality 2 2 2 Evaluation Board Feature Identification Summary 4 2 3 Required Equipment 5 3 Setup Procedure 6 3 1 Install High Speed Data Converter HSDC Pro Software 6 3 2 Install ADC35XXEVM GUI 1 0 Software 6 3 3 Connect the ADC368xEVM and TSW1400EVM 6 3 4 Connect the Power Supply and Mini USB Connections 7 3 5 Connect the Clocks and A...

Страница 2: ...ware modifications 2 1 ADC368xEVM Functionality The ADC368xEVM receives power from the USB 2 0 5 V rail and is then converted to 3 3 VDC and 1 8 VDC The ADC receives 1 8 VDC from the TPS62231 DC DC converter The power consumption of the 1 8 V rail can be monitored using the INA226 in the ADC35xxEVM GUI USB to SPI communication is established using the FTDI FT4234H The ADC clocks can be supplied ex...

Страница 3: ...EVM block diagram Balun input Figure 2 2 ADC36xxEVM block diagram FDA input www ti com Equipment SBAU360 DECEMBER 2020 Submit Document Feedback ADC368xEVM Evaluation Module 3 Copyright 2020 Texas Instruments Incorporated ...

Страница 4: ...test point labeled 5 EXT The USB data connection will still be connected for SPI communications J13 is tied to the REFBUF pin It can be left floating or can be tied to 1 8V shunt pins 2 3 for normal operation J14 is tied to the PDN SYNC pin It can be left floating for tied to ground shunt pins 1 2 for normal operation To power down the ADC tied to 1 8V shunt pins 2 3 The ADC may also be powered do...

Страница 5: ...s the following generators Rohde Schwarz SMA100A Rohde Schwarz SMA100B A bandpass filter is required for the analog input signal due to most signal generators addition of phase noise or spurious components A bandpass filter should also be used for the sample clock input The DCLKIN input does not require a bandpass filter If bandpass filters are not used then the true performance of the ADC may not...

Страница 6: ...wnload and install the HSDC Pro Patch This patch copies all the INI files required to the HSDC pro directory 3 2 Install ADC35XXEVM GUI 1 0 Software Download the ADC35XXEVM GUI 1 0 software from the EVM tool folder at ADC3683EVM Extract and run the executable file and accept the default installation options 3 3 Connect the ADC368xEVM and TSW1400EVM Connect the ADC368xEVM FMC connector to J4 of the...

Страница 7: ...n the same for all ADC modes For the sample clock ADC3683EVM set a signal generator to 65 MHz at a power level of 10 dBm Connect to the SMA connector J4 A bandpass filter for the sample clock is recommended for best AC performance of the ADC368xEVM For the DCLKIN clock ADC3683EVM set a signal generator to 292 5 MHz at a power level of 10 dBm A bandpass filter is not required for the DCLKIN clock E...

Страница 8: ... button switch S1 Also a software reset may be performed at any time to reset the ADC registers to their default state Figure 4 1 ADC35xx Software Reset ADC GUI Configuration www ti com 8 ADC368xEVM Evaluation Module SBAU360 DECEMBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Страница 9: ...de Sample rate and DCLKIN examples ADC3663EVM ADC3662EVM Interface Mode DCLKIN multiplier Example Sample Clock Required DCLKIN Frequency 2 Wire 4 65 MSPS 260 MHz 1 Wire 8 32 MSPS 256 MHz 1 2 Wire 16 10 MSPS 160 MHz For this example ensure that the sampling clock J9 and DCLKIN J7 are connected before launching the ADC35XX EVM GUI In this example for the ADC3683EVM the sampling clock is 65 MHz and t...

Страница 10: ...e 4 2 ADC35xx EVM GUI settings for 2W Bypass Mode ADC GUI Configuration www ti com 10 ADC368xEVM Evaluation Module SBAU360 DECEMBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Страница 11: ...Click OK for the no firmware loaded prompt Select ADC3683_2W_18bit to load firmware and click Yes Figure 4 4 HSDC Pro ini file selection for 2W 18 bit Bypass Mode Enter 65M in the box that says ADC Output Data Rate since the ADC is sampling at 65 MSPS www ti com ADC GUI Configuration SBAU360 DECEMBER 2020 Submit Document Feedback ADC368xEVM Evaluation Module 11 Copyright 2020 Texas Instruments Inc...

Страница 12: ...get Frequency 5 MHz used in this example Click Capture The analog input signal power may need to be adjusted to reach 1 dBFS ADC GUI Configuration www ti com 12 ADC368xEVM Evaluation Module SBAU360 DECEMBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Страница 13: ...e 4 65 MSPS 2 130 MHz 1 Wire 8 32 MSPS 8 32 MHz 1 2 Wire 16 10 MSPS 32 5 MHz For this 16x Real Decimation example apply a 65 MHz signal to J9 sample clock and a 18 28125 MHz signal to J7 DCLKIN External ADC sampling clock source and DCLKIN source must be frequency locked If this is not performed the captured data will appear scrambled If using the onboard clocking option the sampling clock and DCL...

Страница 14: ...683_2W_18bit to load firmware and click Yes Figure 4 5 Real Decimation HSDC Pro INI File 2W 18bit Click on the cog next to ADC Output Data Rate In the new dialogue box enter 65M in ADC Sampling Rate Enter 1M in ADC Input Frequency Enter 16 in Decimation Click OK Click Capture ADC GUI Configuration www ti com 14 ADC368xEVM Evaluation Module SBAU360 DECEMBER 2020 Submit Document Feedback Copyright 2...

Страница 15: ...l Real Decimation Figure 4 7 HSDC Pro 16x Real Decimation FFT 2W 18 bit www ti com ADC GUI Configuration SBAU360 DECEMBER 2020 Submit Document Feedback ADC368xEVM Evaluation Module 15 Copyright 2020 Texas Instruments Incorporated ...

Страница 16: ...l to J9 sample clock and a 18 28125 MHZ signal to J7 DCLKIN External ADC sampling clock source and DCLKIN source must be frequency locked If this is not performed the captured data will appear scrambled If using the onboard clocking option the sampling clock and DCLKIN are frequency locked Apply a 10 MHz signal to J2 ensure bandpass filter is used to reduce harmonics and noise of signal generator ...

Страница 17: ...omplex to load firmware and click Yes Figure 4 8 Complex Decimation HSDC Pro INI file Click on the cog next to ADC Output Data Rate In the new dialogue box check the Enable box Under ADC Sampling Rate enter 65M Under ADC Input Frequency enter 10M Under NCO enter 9 9M Under Decimation enter 32 www ti com ADC GUI Configuration SBAU360 DECEMBER 2020 Submit Document Feedback ADC368xEVM Evaluation Modu...

Страница 18: ...og Parameters 32x Complex Decimation Mode Select Complex FFT Press Capture ADC GUI Configuration www ti com 18 ADC368xEVM Evaluation Module SBAU360 DECEMBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Страница 19: ...e 4 10 HSDC Pro 32x Complex Decimation 2W 18 bit www ti com ADC GUI Configuration SBAU360 DECEMBER 2020 Submit Document Feedback ADC368xEVM Evaluation Module 19 Copyright 2020 Texas Instruments Incorporated ...

Страница 20: ...ock spurs and broad band phase noise in order to acheive full ADC performance Figure 5 1 ADC3683EVM onboard clocking CDCE6214 65 MHz sample clock 292 5 MHz DCLKIN The following section shows how to configure and program the ADC368xEVM for onboard clock operation for Real Decimation Mode Onboard clocking can be used for Bypass and Complex Decimation modes as well and uses similar procedures that ha...

Страница 21: ...ple Clock Modification DNI R46 R47 Install R41 R51 0 Ω resistor Figure 5 2 ADC36xxEVM Onboard Sample clock modifications Onboard DCLKIN Modification Install R60 and R62 0 Ω resistor DNI R35 and R36 www ti com Onboard Clocking Hardware Setup SBAU360 DECEMBER 2020 Submit Document Feedback ADC368xEVM Evaluation Module 21 Copyright 2020 Texas Instruments Incorporated ...

Страница 22: ... 3 ADC368xEVM Onboard DCLKIN modifications Onboard Clocking Hardware Setup www ti com 22 ADC368xEVM Evaluation Module SBAU360 DECEMBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Страница 23: ... observed in the GUI is the CDC Clock Enable button must be enabled Green and the Configure CDC button must be clicked The PLL_LOCK LED D1 also illuminates to ensure CDCE6214 has been configured correctly Figure 5 4 AD35xx EVM GUI Onboard Clock 16x Real Decimation www ti com Onboard Clocking Hardware Setup SBAU360 DECEMBER 2020 Submit Document Feedback ADC368xEVM Evaluation Module 23 Copyright 202...

Страница 24: ...ocedure shows how to configure the FDA single ended to diferential conversion for CHA The same procedure can be performed for CHB with the respective component designators The edge launched SMA connector J1 receives the single ended analog input signal R1 can be replaced with a capacitor for AC coupling to FDA Modify the following components to complete path to FDA located on top of EVM Install R1...

Страница 25: ...omponents C52 L11 L12 and C53 can be adjusted as the application requires The termination resistors R80 R81 R89 and R90 can be adjusted according to the source impedance Figure 6 3 FDA schematic For further information on the THS4541 FDA please refer to the THS4541 datasheet www ti com FDA Configuration SBAU360 DECEMBER 2020 Submit Document Feedback ADC368xEVM Evaluation Module 25 Copyright 2020 T...

Страница 26: ...onsumption on the front page of the ADC35XX EVM GUI Click the Measure Power button to refresh the current values This feature is useful for determining what mode sampling speed offers the best power consumption for your application needs Figure 7 1 ADC36xxEVM Power Meter ADC36xxEVM Power Monitor www ti com 26 ADC368xEVM Evaluation Module SBAU360 DECEMBER 2020 Submit Document Feedback Copyright 202...

Страница 27: ...The digital ramp pattern is now enabled on the ADC The output of the ADC is now an 18 bit incrementing ramp pattern Figure 8 1 ADC36xxEVM 18 bit Ramp Pattern In HSDC Pro the ramp pattern can now be seen when data is captured These same steps apply to any data output mode Bypass Real Decimation and Complex Decimation It may be necessary to increase the capture sample size to 524k to capture the ent...

Страница 28: ...ples Trademarks Microsoft and Windows are registered trademarks of Microsoft Corporation All trademarks are the property of their respective owners Trademarks www ti com 28 ADC368xEVM Evaluation Module SBAU360 DECEMBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated ...

Страница 29: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Страница 30: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Страница 31: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Страница 32: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Страница 33: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Страница 34: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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