Texas Instruments ADC1xD1x00CVAL Series, Руководство пользователя

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4 SNAU212 – June 2017
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ADC1xD1x00CVAL Board User’s Guide
Three key requirements for the sampling clock signal generator are low distortion, broad band noise, and
phase noise. Even the highest quality signal generator will also produce harmonics, which the ADC
performance is very sensitive to. Therefore, a bandpass filter, which can be tuned to the desired sampling
clock frequency, will improve the performance of the system. In addition to this, the bandpass filter will
reduce broadband noise and increase the system performance.
The logic analyzer should be able to capture differential LVDS signals at high speed, as determined by the
sampling clock speed and ADC Demux Mode. In general, the Output Data Rate per Bank can be
determined as follows:
Table 1. Output Data Rate Per Bank by Mode
MODE OUTPUT DATA RATE PER BANK [MSPS]
DES 1:1 Non-Demux Fs/2
DES 1:2 Demux Fs/4
Non-DES 1:1 Non-Demux Fs
Non-DES 1:2 Demux Fs/2
For example, the ADC12D16x0 will generate data at the following rates:
Table 2. ADC12D16x0 Output Data Rate Example
MODE FCLK [MHz] FS [MSPS]
OUTPUT DATA RATE PER BANK
[MSPS]
DES 1:1 Non-Demux 1600 3200 1600
DES 1:2 Demux 1600 3200 800
Non-DES 1:1 Non-Demux 1600 1600 1600
Non-DES 1:2 Demux 1600 1600 800
The EVAL board is designed to be used with the Samtec ASP-65067-01 for the logic analyzer probe
connection to the Keysight E5379A Differential Probe Adapter. There is also a footprint for the Keysight
E5405A Pro Series Soft Touch Connectorless Probe, but this option is not recommended, as the signal
integrity is better through the Samtec connector.
2.2 Optional Lab Equipment
If the EVAL board is being used in Extended Control Mode (ECM), then it is also necessary to have a
system which can write to the SPI. One option is the Aardvark I2C/SPI Host Adapter and accessories.
• Aardvark I2C/SPI Host Adapter
http://www.totalphase.com/products/aardvark_i2cspi/
• Level Shifter Board
http://www.totalphase.com/products/level_shifter/
• 10-pin Split Cable
http://www.totalphase.com/products/split_cable/
3 Driving the Clock and Inputs
3.1 Driving the Sampling Clock
The CLK± SMA inputs are connected directly to the ADC; they must be driven AC-coupled and
differentially. Therefore, a set of DC blocks is required at the input. To convert a single-ended signal to
differential, a National Anaren balun board (400 MHz to 3 GHz) may conveniently be used.