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Appendix D

SLAU640 – April 2019

Analog Inputs

A 3dB attenuation pad is added between the inputs and the ADC. The 3 dB pad helps with the flatness of
the frequency response.

Figure D-2. 3 dB attenuation pad

Содержание ADC12DJ5200RF

Страница 1: ...ADC12DJ5200RF Evaluation Module User s Guide Literature Number SLAU640 April 2019 ...

Страница 2: ...l Generator RF Outputs 12 3 9 Open the ADC12DJ5200RFEVM GUI and Program the ADC and Clocks 12 3 10 Calibrate the ADC Device on the EVM 13 3 11 Open the HSDC Software and Load the FPGA Image to the TSW14J57EVM 14 3 12 Capture Data Using the HSDC Pro Software 14 4 Device Configuration 17 4 1 Supported JESD204C Device Features 17 4 2 Tab Organization 17 4 3 Low Level Control 18 5 Troubleshooting the ...

Страница 3: ...l Device Parameters Dialog Box 16 4 1 Low Level Register Control Tab 18 B 1 ADC12DJ5200RFEVM Clocking System Block Diagram 22 B 2 Onboard Clocking System Block Diagram 23 B 3 External Reference Clocking System Block Diagram 24 B 4 External Clock Configuration 24 B 5 Onboard Clocking Configuration 25 D 1 Analog Input Path 28 D 2 3 dB attenuation pad 29 List of Tables 4 1 Supported and Non Supported...

Страница 4: ...e and EVM are synonymous with the ADC12DJ5200RFEVM In the following sections of this document the ADC12DJ5200RF evaluation board is referred to as the EVM and the ADC12DJ5200RF device is referred to as the ADC device This document also includes an electrical schematic printed circuit board PCB layout drawings and a parts list for the EVM Trademarks K L Microwave is a trademark of K L Microwave Mic...

Страница 5: ... following important features Transformer coupled signal input network allowing a single ended signal source from 500 kHz to 9 GHz The LMX2594 clock synthesizer generates the ADC sampling clock The LMK04828 LMK61E2 and LMX2594 onboard system clock generator generates SYSREF and FPGA reference clocks for the high speed serial interface Transformer coupled clock input network to test the ADC perform...

Страница 6: ...RFEVM board is quickly and easily captured with the TSW14J57EVM data capture boards NOTE The TSW14J57EVM cannot be used for JMODES 30 to 39 that use 64b 66b encoding or serial rates above 15 Gbps The TSW14J57EVM captures the high speed serial data decodes the data stores the data in memory and then uploads it to a connected PC through a USB interface for analysis The High Speed Data Converter Pro ...

Страница 7: ...yright 2016 Texas Instruments Incorporated 7 SLAU640 April 2019 Submit Documentation Feedback Copyright 2019 Texas Instruments Incorporated Equipment Chapter 2 SLAU640 April 2019 Equipment This section describes how to setup the EVM on the bench with the proper equipment to evaluate the full performance of the ADC device 2 1 Evaluation Board Feature Identification Summary Figure 2 1 EVM Feature Lo...

Страница 8: ...n the EVM evaluation kit but is required for evaluation of this product TSW14J57EVM data capture board and related items High Speed Data Converter Pro software Also install the HSDCpro Patch v5 00 02 exe to download ADC12DJ5200RF INI files to the PC Make sure the install location matches Figure 2 2 Figure 2 2 HSDCpro Patch to Install INI Files PC computer running Microsoft Windows 7 or 10 Two low ...

Страница 9: ...ixed BPF Signal path cables SMA or BNC or both SMA and BNC By default the ADC12DJ5200RFEVM has an external clocking solution A few small board modifications enable onboard clocking If onboard clocking is used the following equipment is recommended One low noise signal generators TI recommends similar models to the analog input source A bandpass filter for the analog input TI recommends a filter si...

Страница 10: ...ata Converter HSDC Pro Software 1 Download the most recent version of the HSDC Pro software from www ti com tool dataconverterpro sw Follow the installation instructions to install the software 2 Download and install the patch which will copy all the INI files required to the HSDCpro directory 3 2 Install the Configuration GUI Software 1 Download the Configuration GUI software from the EVM tool fo...

Страница 11: ...s a Trilithic tunable bandpass filter to filter the signal from the generator Configure the signal generator for 2897 MHz 6 dBm When External Clocking is Used a Connect a signal generator to the DEVCLK input of the EVM through a bandpass filter This signal generator must be a low noise signal generator TI recommends a Trilithic tunable bandpass filter to filter the signal coming from the generator...

Страница 12: ...vice drivers See the TSW14J57EVM user s guide for specific instructions 3 7 Turn On the ADC12DJ5200RFEVM Power Supplies and Connect to the PC 1 Turn on the 12 V power supply to power up the EVM 2 Connect the EVM to the PC with the mini USB cable 3 8 Turn On the Signal Generator RF Outputs Turn on the RF signal output of the signal generator connected to VIN If external clocking is used turn on the...

Страница 13: ...p for each device is provided in the device data sheet ADC12DJ5200RF 10 4 GSPS Single Channel or 5 2 GSPS Dual Channel 12 bit RF LMK0482xB Ultra Low Noise JESD204B Cmplnt Clck Jitter Cleaner w Dual Loop PLLs and LMX2594 15 GHz Wideband PLLatinum RF Synthesizer respectively 1 Open the ADC12DJ5200RFEVM GUI 2 Select the external clock as the clock source 3 Enter Fs 5200 MHz MSPS as the external Fs se...

Страница 14: ...bration use the following steps Navigate to the JESD204C tab and click on JESD Block Enable to stop the JESD204C block Navigate back to the Control tab and click on Enable Calibration Block to disable calibration and allow setting changes If background offset calibration was enabled click on Enable Background Offset Cal to disable the feature Click on Enable Background Cal to disable the feature C...

Страница 15: ...t with the Bandwidth Integration Markers from the Test Options file menu The Channel Power test is also useful For analyzing only a subset of the captured data set the Analysis Window samples setting to a value less than the number of total samples captured and move the green or red markers in the small transient data window at the top of the screen to select the data subset of interest Figure 3 4...

Страница 16: ... Data Using the HSDC Pro Software www ti com 16 SLAU640 April 2019 Submit Documentation Feedback Copyright 2019 Texas Instruments Incorporated Setup Procedure Figure 3 5 Additional Device Parameters Dialog Box ...

Страница 17: ...ged re enable the JESD204 block Table 4 1 Supported and Non Supported Features of the JESD204C Device JESD204C Feature Supported by ADC Device Supported by TSW14J57EVM Supported by TSW14J58EVM Number of lanes per link L L 1 2 3 4 6 8 1 L 1 2 3 4 6 8 supported L 1 2 3 4 6 8 supported Total number of lanes active 2 4 6 8 12 16 2 4 6 8 12 16 2 4 6 8 12 16 Number of frames per multiframe K Kmin 3 256 ...

Страница 18: ... summary with the value in the Write Data field Write all button Update all registers shown in the register map summary with the values shown in the Register Map summary Read register button Read from the register highlighted in the Register Map summary and display the results in the Read Data field Can be used to re synchronize the GUI with the state of the hardware Read all button Read from all ...

Страница 19: ...nager and verify that a USB serial device is recognized when the EVM is connected to the PC Verify that the green USB Status LED light in the top right corner of the GUI is lit If it is not lit click the Reconnect FTDI button Try restarting the configuration GUI Configuration GUI is not able to connect to the EVM Use the free FT_PROG software from FTDI chip and verify that the onboard FTDI chip is...

Страница 20: ... Reference Documents ADC12DJ5200RF device data sheet TSW14J57EVM user s guide TSW14J56EVM user s guide High Speed Data Converter Pro GUI User s Guide also available in the help menu of the software LMK04828 data sheet LMX2594 data sheet FTDI USB to Serial Driver Installation Manual www ftdichip com Support Documents InstallGuides htm A 2 TSW14J57EVM Operation Refer to the TSW14J57EVM user guide fo...

Страница 21: ...e output by the JESD204 transmitter ADC device is configured using the K parameter on the JESD204C tab in the Configuration GUI This parameter must be matched by the receiving device and the SYSREF frequency must also be programmed to a compatible frequency Ensure that the K value complies with the K Min and Step values for the selected JMODE Refer to the ADC12DJ5200RF operating modes table in the...

Страница 22: ...By default the EVM is configured to use the external clock option The user provide and external clock signal for both the ADC sampling clock DEVCLK at J10 and also the Reference clock REF CLK at J17 which feed into the LMK04828 and is used in clock distribution mode and provides the FPGA reference clock FPGA SYSREF signal and ADC SYSREF signal If coherent sampling is desired the external clocking ...

Страница 23: ...he required clocking is generated on the EVM and no external clock signal is required The LMK61E2 generates the reference frequency LMK00304 make two copies of the reference signal and sends the one copy to LMX2594 to generate the sampling clock for the ADC and LMK04828 uses the second copy in clock distribution mode to provides the FPGA reference clock FPGA SYSREF signal and ADC SYSREF signal Fig...

Страница 24: ...tion The Reference clock J17 is provided by an external source The LMK00304 make two copies of the reference signal and sends the one copy to LMX2594 to generate the sampling clock for the ADC and LMK04828 uses the second copy in clock distribution mode to provides the FPGA reference clock FPGA SYSREF signal The ADC SYSREF signal is generated by the LMX2594 Figure B 3 shows the block diagram of ex...

Страница 25: ...EVM for Optional Clocking Support 25 SLAU640 April 2019 Submit Documentation Feedback Copyright 2019 Texas Instruments Incorporated HSDC Pro Settings for Optional ADC Device Configuration Figure B 5 Onboard Clocking Configuration ...

Страница 26: ...dard FMC polarity Table C 1 ADCxxDJxx00RFEVM Signal Routing JESD204C Output Link LID FMC Pins FMC Signal Names 1 DA0 A 0 A10 A11 DP3_M2C DA1 A 1 C6 C7 DP0_M2C DA2 A 2 A6 A7 DP2_M2C DA3 A 3 A2 A3 DP1_M2C DB0 B 0 B12 B13 DP7_M2C_INV DB1 B 1 A14 A15 DP4_M2C_INV DB2 B 2 B16 B17 DP6_M2C_INV DB3 B 3 A18 A19 DP5_M2C_INV DA4 A 4 Z12 Z13 DP11_M2C DA5 A 5 Y10 Y11 DP10_M2C DA6 A 6 B8 B9 DP8_M2C DA7 A 7 B4 B5...

Страница 27: ... 2019 Analog Inputs Table D 1 provides the different settings for setting the analog inputs path Table D 1 Analog Input Path Coupling Input SMA to Use R2 R6 R10 R14 R1 R8 R9 R16 AC default S E Balun 500kHz to 9GHz INA J4 INB J7 0 Ω DNI AC Differential INAP J5 INAM J3 INBP J6 INBM J8 DNI 0 1 µF DC Differential INAP INAM INBP INBM DNI 0 Ω ...

Страница 29: ...Submit Documentation Feedback Copyright 2019 Texas Instruments Incorporated Analog Inputs A 3dB attenuation pad is added between the inputs and the ADC The 3 dB pad helps with the flatness of the frequency response Figure D 2 3 dB attenuation pad ...

Страница 30: ...rnal Reference clock signal is selected default Uninstalled Onboard reference signal LMK61E2 is selected J18 When hardware calibration trigger option is enabled The ADC s calibration routine is can be enable using external signal Installed ADC s calibration routine is triggered Uninstalled ADC s calibration routine is not triggered default J19 Selects the source for SPI signals Installed SPI signa...

Страница 31: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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