Click the
Program
button to complete the FPGA configuration with the bitfile.
Figure 7-11. Program Device With the bit File
In the Vivado TCL console, execute the following:
• cd c:/AlphaData_ADC12DJ3200_Demo
• source setup_new.txt
Switch back to the ADC12DJ3200EVM-CVAL GUI.
Navigate to the JESD204B tab and click on the JSYNC_N Sync Request button (it should now be off, as
shows).
Switch back to the Vivado setup.
In the Vivado TCL console, execute the following:
cd c:/AlphaData_ADC12DJ3200_Demo
source capture_new.txt
The FPGA will now be doing continuous captures of the ADC data.
Alpha-Data ADC12DJ3200EVMCVAL Start-up Instructions
20
ADC12DJ3200EVMCVAL With Alpha Data Xilinx
®
Kintex Ultrascale Space
Development Kit
SLAU833A – MAY 2020 – REVISED OCTOBER 2020
Copyright © 2020 Texas Instruments Incorporated
