Alternate Hardware Configurations
10
SLAU715 – February 2017
Copyright © 2017, Texas Instruments Incorporated
ADC08060 Evaluation Module
4
Alternate Hardware Configurations
This section describes alternate hardware configurations in order to achieve better results or to more
closely mimic the system configuration.
4.1
Clocking Options
The default clocking mode uses a crystal clock oscillator to generate the ADC sampling clock and FPGA
clocks. An alternative option is described in the following section.
4.1.1
External ADC Sampling Clock
An external clock can be used as the sampling clock for the ADC. For this option, the oscillator must be
bypassed with a jumper (JP2) by changing its position to SHUNT 2–3. Provide a filtered, low-noise 60-
MHz signal from an RF generator to the SMA connection on the EVM (J3).
4.2
Voltage Reference Options
The default configurations uses a LM8272 rail-to-rail precision op amp to drive the reference voltage. By
default, the top reference voltage is set to 1.9 V and the bottom voltage is set to 0.3 V. Alternative options
are described in the follow sections.
4.2.1
External Voltage Reference
An external voltage reference can be used to supply the reference voltage to the ADC. For this option,
jumper VRT (JP9) and VRB (JP8) must be pulled out and left OPEN. Apply a top voltage reference at the
test point VRTP (TP5) and bottom reference at VRBP (TP6). If the desired voltage references are 3 V and
GND, change jumpers JP9 and JP8 to SHUNT 2-3.
4.2.2
Divider Resistor Modification
If the LM8272 is desired to drive the reference voltages, but at a different range, the divider resistors (R1
and R3) can be changed to suit the reference voltage needed. R1 and R3 are larger for easy soldering
modifications.
