TPCE636 User Manual Issue 1.0.2
Page 47 of 104
Clocking
7.6
7.6.1 FPGA Clock Sources
As a central clock generator of the TPCE636 the Si5338 clock generator is used. This provides all necessary
clocks for the User FPGA and the Configuration FPGA.
The following figure depicts an abstract User FPGA clock flow.
Si514
prog. XO
Si5338 Clock Generator
BCC
Kintex-7
DDR3
PCIe Switch
Bank
33
32MHz
Oscillator
2
0
0
M
H
z
R
E
F
_
C
L
K
8
8
.8
8
9
M
H
z
M
C
B
_
C
L
K
1
5
6
.2
5
M
H
z
1
0
0
M
H
z
PCIe
to
PCI
25 MHz
PCI-CLK
100 MHz
User definied
open
100 MHz
DDR3 Memory Clocks
MGT Ref. Clocks
E
M
C
C
L
K
SPI
C
C
L
K
2 - 133
MHz
internal
DIV
EN
Config Clocks
open
P14
8 x
Dual-ADC
8
x
C
L
K
_
IN
ADC Clocks
Bank 115
Bank 16
Bank 116
C
L
K
_
M
G
T
1
0
5
M
H
z
4 x CLK
1
5
6
M
H
z
D
e
fa
u
lt
8
x
C
L
K
_
O
U
T
P15
53.2 MHz
Bank 12, 13
Bank 14, 15
Figure 7-5 : FPGA Clock Sources
