TAMC900 User Manual Issue 2.0.1
Page 15 of 71
4.1 Channel Logic
The channel logic is implemented for every channel group. It realizes the data synchronization between the
internal processing clock and the ADC sample clock domain. This is necessary because these clocks can
have an arbitrary ratio to each other. Only the limits of the ADCs have to be considered.
The ADCs have an operating frequency of 1 MHz up to 105 MHz.
Besides this the sign extension is performed in this unit. This has been implemented to simplify the data
processing out of the target memory by mapping the ADC values into legal data types. The sign-extension
method is described below.
•
In 2-th complement the ADC sign bit (13) is mapped onto the additional bits 14 and 15.
•
In binary offset format the ADC sign bit (13) is mapped onto bit 15 and the bits 13 and 14 are set to
zero.
A
IN
+ - A
IN
-
(2V Range)
OF
Data
(Offset Bin.)
Data
(2’s Compl.)
>+1.000000V
1 0x9FFF
0x1FFF
+0.999878V 0 0x9FFF
0x1FFF
+0.999756V 0 0x9FFE
0x1FFE
... ...
... ...
+0.000122V 0 0x8001
0x0001
0.000000V 0 0x8000
0x0000
-0.000122V 0 0x1FFF
0xFFFF
-0.000244V 0 0x1FFE
0xFFFE
... ...
... ...
-0.999878V 0 0x0001
0xE001
-1.000000V 0 0x0000
0xE000
<-1.000000V 1
0x0000
0xE000
Table 4-2 : ADC Data Format with Sign Extension
