VEEK-MT-SoCKit User Manual
March 17, 2014
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After the configuration is complete, the CMOS sensor starts capturing and sending out image data
stream. The CMOS Capture block extracts the valid pixel data stream based on the synchronous
signals from the CMOS sensor. The data stream is generated in Bayer Color Pattern format. It is
converted to RGB data stream within the RAW2RGB block.
The Multi-Port DDR3 SDRAM Controller then acquires the RGB data stream and writes it to the
DDR3 SDRAM, which acts as a frame buffer. The Multi-Port DDR3 SDRAM Controller has two
write ports and read ports with 128-bit data width each. The writing clock is same as the CMOS
sensor pixel clock. The reading clock is provided by the LCD Controller, which is 33MHz.
Finally, the LCD controller fetches the RGB data from the buffer and displays it on the LCD panel
continuously. Because the resolution and timing of the LCD is compatible with WVGA@800*480,
the LCD controller generates the same timing, and the frame rate can achieve approximately 25
fps
.
For better visual effect, the CMOS sensor is configured to enable the left right mirror mode. Users
can disable this functionality by modifying the value of associated register written to the CMOS
controller chip.
Figure 4-6 Block diagram of the digital camera design
Demonstration Source Code
Project directory: System-CD\Demonstrations\FPGA\SoCKit_Camera
Bit stream: SoCKit_Camera.sof
