NL865B1 HW Design Guide
1VV0301450 Rev. 1
Page
45
of
72
2017-11-20
WARNING:
During power up the GPIOs may be subject to transient glitches.
5.6.1.
Using a GPIO as INPUT
The GPIO pads, when used as inputs, can be connected to a digital output of another
device and report its status, provided this device has interface levels compatible with the
1.8V CMOS levels of the GPIO. If the digital output of the device to be connected with the
GPIO input pad has interface levels different from the 1.8V CMOS, then it should be
buffered with an open collector transistor with a 47K pull up to VAUX.
Any of the GPIO's 1 => 8 can be used as an interrupt source. User can configure the
interrupt for either faling or rising edge
Any of the GPIO's 1 => 8 can be used as a wakeup source thus waking up the module
from sleep. User can configure the wakeup for either faling or rising edge
NOTE:
In order to avoid a back powering effect it is recommended to avoid
having any HIGH logic level signal applied to the digital pins of the
NL865B1 when the module is powered off or during a
powerup/reboot transition.
Using bidirectional level translators which do not support High Z
mode during power off is not recommended.
The VAUX /PWRMON pin can be used for input pull up reference.
