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S42 Hardware User Guide
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Page 29 of 62
C
L
= (C1+C
pin
+C
s
) * (C2+C
pin
+C
s
) / (C1+C2+2*C
pin
+2*Cs), or
C1, C2 = (2*C
L
– C
pin
– C
s
)
C
pin
: see
C
s
: stray capacitance, depends on layout
Figure 11: S42 connection of external XTAL
3.10
Test Mode
For homologation purposes the ability of test mode operation like “S42_Testmode”
or “Direct two wire UART Testmode” (DTM) is mandatory. The Direct Test Mode (as
defined by the Bluetooth SIG) and S42_Testmode are part of the S42
TIO-Firmware. Please refer to tbd.
For enabling the different test modes the S42 provides two IO pins.
•
The pin Testmode is low active. Active in the following table means connect to GND.
•
The pin Boot0 is high active. Active in the following table means connect to VDD.
•
The other two combinations start the bootloader for firmware update of the
programmed firmware. These two modes are not scope of this document.
Table 6 shows the possible combinations:
Testmode#
Boot0
Mode
Active
Inactive
Testmode
Active
Active
DTM
Inactive
Active
Start Bootloader
Inactive
Inactive
Firmware Update
Table 6: Testmode# / Boot0 Logic
XL-IN
S42
A-6
Slow Clock
XL-OUT
A-5
32,768kHz
CL: 9pF
C1
C2
C1, C2 ~ 12pF