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Содержание TS 806

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Страница 2: ...Te eVideo TS 806 TS 806C TS 806H TS 806120 and TS 806HI20 Maintenance Manual TeleVideo Systems Inc 1170 Morse Avenue Sunnyvale California 94086 408 745 7760...

Страница 3: ...eserves the right to make improvements to products without incurring any obligations to incorporate such improvements in products previously sold Specifications and information contained herein are su...

Страница 4: ...b Section Computer Systems Division Limited Warranty 1 TS 806 Theory of Operation includes TS 806H TS 806 20 and TS 806H 20 2 TS 806C Theory of Operation 3 System Repair Price and Spare Parts Price Li...

Страница 5: ...factured by TeleVideo only the warranty if any given by the manufacturer thereof applies EXCLUSIONS This limited warranty does not cover losses or damage which occurs in shipment to or from Buyer or C...

Страница 6: ...n describes the hardware layout functions and operations Section 1 0 2 0 3 0 4 0 s o 6 0 7 0 8 0 TABLE OF CONTENTS Title Introduction General Description Function Circuit Description Connect r Configu...

Страница 7: ...20 megabyte Winchester drive in the same style cabinet as the TS806 Both systems use the WD lOOO disk interface board The TS806 can be expanded with the TS 806H and the TS806 20 is expanded with the...

Страница 8: ...e ZSOA DMA Direct memory access controller chip is used for direct transfer of data between memory and peripheral I O like floppy disk Winchester hard disk etc f Memory Main memory available to user i...

Страница 9: ...power up or reset and are not acces sible by the users After the initial program in the ROM is run upon power up or reset the dynamic memory area address 00 16 K hex is switched on so that the whole 6...

Страница 10: ...Hiud DiSk MiJl Floppy Disk Dl ives Winchester Htltd Disk COJltrolier Centronic type PriJl ter Interface DRAM 64kX8 l80A DMA l80A CPU O l AI RATE eTC 0 RS232C 1 RS232C I II l J 2 BAUD RATE t L J SwrT...

Страница 11: ...0 0 X X X 40 WDC Reset Winchester Disk Soft Reset 0 1 0 1 0 X 0 0 50 510 0 ChA Data Reg 1 0 52 Com Stat Reg 0 1 51 Ch B Data Reg 1 1 53 Com Stat Reg 0 1 1 0 0 X X X 60 Baud Rate Load 0 1 1 1 0 X X X 7...

Страница 12: ...ector Reg 1 1 B3 Data Reg 1 1 0 0 0 X 0 0 CO PIC Ch 0 CTC User Option 0 1 C1 Ch 1 1 0 C2 Ch 2 1 1 C3 Ch 3 1 1 0 1 0 X 0 0 DO PIO Ch A Data Reg 1 0 D2 Corn Stat Reg 0 1 D1 Ch B Data Reg 1 1 D3 Corn Sta...

Страница 13: ...h POSe Baud Rate 4 3 2 1 19 2 KBaud 0 0 0 0 9 6 KBaud 0 0 0 1 4 8 KBaud 0 0 1 0 2 4 KBaud 0 0 1 1 1 2 KBaud 0 1 0 0 600 Baud 0 1 0 1 300 Baud 0 1 1 0 150 Baud 0 1 1 1 75 Baud 1 0 0 0 Table 2 Baud Rate...

Страница 14: ...and data bus float and the control signal outputs are in active The CPU returns to normal operation after two internal T cycles Reset clears the PC register so the register now contain s a value of 0...

Страница 15: ...e the ROM and SRAM When the ROM and SRAM are enabled CAS signal for dynamic RAM column address goes inactive disabling dynamic RAM OOH l6KH so only ROM and SRAM are active During read write operations...

Страница 16: ...d previously when dynamic RAM is enabled it activiates CAS signal so that all DRAM locations can be accessed by the user During refresh only RAS signal is acti vated and one whole row is refreshed at...

Страница 17: ...READ Cyel I WRITE CYCL J I I Ao A 5 MREQ V v ROMCE Y GOns 7YI YI DATA 1 V ROM 9071S YVlo x WR IOOll 111 x r SRAH CS 1 I 23071S 1 l1 X DATA I 701lS n i71 WAIT V SRAM Figure 6 Read Write on ROM and SRA...

Страница 18: ...S DATA ClK Ao I s ns m II It ISO 1 lS 7Yl X IOOl l m 00 1I57n X f I O llSm X I I 9 TlS l1lO X 11 70 l1s 7Il X 71 m x I 90113 me If J Figure 7 Instruction Fetch from DRAM MREQ 10 RD WR DATA Figure 8 Re...

Страница 19: ...s soon as the current CPU machine cycle is terminated and then sends out BUSAK signal to indicate that DMA can control these signals Figure 9 illustrates the BUSREQ and BUSAK BAI timing The RDY line i...

Страница 20: ...__ X ______ MREQ rv RD r v DATA rv Figure 10 RDY Line in Burst Mode Refer to I O Operation for precise timing RDY J V I 6USR N ___________ J r BAY _________ J r X Ao Als X _ c x r rv r v MREQ RI DATA...

Страница 21: ...ficient time for an I O port to complete a read write operation One SIO A82 is for RS232 interfaces and its related chips are 75188 for output and 75189 for input The other 3 SIO s A61 A83 A84 are for...

Страница 22: ...that the data register contains assembled data in the read oper ation or the data register is empty in the write operation This signal is reset when serviced by the system through reading or loading t...

Страница 23: ...DMA read operation WD 1000 controller board is used for 5 Winchester disk interface As with the floppy disk controller WDe DRQ signal is used to control the RDY line of DMA by being NANDED with other...

Страница 24: ...cs WPRQ WWE r 1 0 READ t MEM WRITf t J T T2 TW l T T I T I T I 200 l s11 l _ l S 7 S I 100 s YrI X Figure 15 woe To Memory Transfer OMA Read Operation I I 20011 S 1 IIAX f 100 1 1 1 I IOIx 25 1 s x Fi...

Страница 25: ...nnector P1 P2 P3 p4 P5 P6 P7 P8 P9 P10 P11 Pl2 P13 Description Power RS232C Service Terminal Interface RS232C Serial Interface Centronics type Printer Interface Winchester Disk Controller Interface Re...

Страница 26: ...2 RS232C Connector P2 3 25 Pin Pin No 1 2 3 4 5 7 8 20 Description DCE P3 Frame Ground Transmit Data Receive Data P3 Receive Data Transmit Data P3 Request to Send Clear to Send Signal Ground Data Carr...

Страница 27: ...lect 0 Drive Select 1 Drive Select 2 Motor On Direction Select Toward Center Off Center Step Composite write Data write Enable Track 00 write Protected Composite Read Data Side 1 Select Ignored by one...

Страница 28: ...2 7 WDAL 3 9 WDAL 4 11 WDAL 5 13 WDAL 6 15 WDAL 7 17 WA 0 19 WA 1 21 WA 2 23 wcs Winchester Chip Select 25 WWE Winchester Read Enable 27 WWAIT 29 WINTRQ Interrupt Request 35 WDRQ Data Request 37 WMR M...

Страница 29: ...ey are connected together Refer to Figure 18 for comparison of two connector pin assignment between 40 pin connector on the board and 36 pin connector on the rear panel which will be hooked up to the...

Страница 30: ...1 34 32 D iJ 7 W9 17 33 35 34 18 35 36 36 Second pin number indicates return ground Pin 37 38 39 and 40 are not connected Ground if no connection Tie high if no connection Description Data strobe Outp...

Страница 31: ...P8 to P12 connectors are 16 pin header type but these are connected to the D type on the rear panel eventually The difference is only due to the different numbering order between those two types Refer...

Страница 32: ...Manufacturer a Signal GND Table 9 D Type Configuration for RS422 b pa to P12 header type 16 pin Pin No Description Description D Board D Board Conn Conn 1 1 Shield 9 2 TXD 2 3 TXD 10 4 RXD 3 5 RXD 11...

Страница 33: ...LED s are used for diagnostic purposes They are lit when the data line goes low The corresponding port address is 00 the data byte assigned to each LED is as follows LED No 1 2 3 4 Data Byte FO Fl F2...

Страница 34: ...the printer interface does not need this signal Connect when the printer interface does not need this signal Connect when the printer interface does not need this signal Connect when the printer inte...

Страница 35: ...All power for the board can be supplied from a single S volt power supply on a separate connector All host to disk data transfers are buffered by onboard RAM to achieve totally asynchronous transfers...

Страница 36: ...nsure the data remains stable during the entire instruction This data selects a read strobe and write strobe through two 1 of 8 decoders U20 and 026 which are alternately enabled by the WC control str...

Страница 37: ...h drives a Schmitt trigger U3l to provide a proper rise fall time on the RESET line of the 8X300 Alternate reset of the processor can be accomplished by dropping MR J5 pin 39 whenever the host wishes...

Страница 38: ...512 bytes 8 2 6 2 Sector Buffering All data read from the disk or written to the disk is passed through the RAM to provide buffering required for asynchronous data transfer between the host and disk T...

Страница 39: ...technique This technique requires clock bits to be recorded only when two successive data bits are missing in the serial data stream This reduces the total number of bits required to record a given am...

Страница 40: ...erefore set to an open loop frequency of 2X RCLK Any variations in this rate due to variations in disk rotational speed must be compensated for by the VCO Instantaneous shifts in data due to the effec...

Страница 41: ...0 to determine the condition of the MFM data stream The data and clocks are now connected to the first stage of the data separator The heart of the data separator is the VCO U2 and associated circuitr...

Страница 42: ...The diode then receives and lower VCO The operating point of the tuning diode CRI is initially set for an open loop VCO frequency of two times RCLK by setting OSC ADJUST and monitoring the VCO output...

Страница 43: ...dition When the circuit is balanced either both pumps are on or both pumps are off producing no net pump up or down 8 3 8 Window Extension Once the VCO has been locked onto the phase of the incoming d...

Страница 44: ...d or data field Whenever SEARCH is dropped the VCO to RCLK divider is once again reset and no RCLKS are produced 8 4 Data Conversion and Checking MFM data which has been separated to form NRZ data and...

Страница 45: ...rcuitry The AMOET signal remains true until the processor again de asserts the SEARCH control line 8 4 2 Serial to Parallel Conversion After an AM has been detected the Serial to Parallel converter U2...

Страница 46: ...read on the disk The polynomial used is X16 X12 X5 1 commonly called the CRC CCITT polynomial During read operations the processor polls the condition of the DRUN circuitry When DRUN is true it begin...

Страница 47: ...a convenient latching function for the CRCOK flag which mains true for at least 1 byte after the last CRC check byte gi ing the processor time to read the flag The data clock and BDONE are supplied t...

Страница 48: ...used as the clock for the CRC device Whenever it is desired to write a repetitive string of identical data bytes the processor can simply ignore the BOONE flag and permit the device to reload the dat...

Страница 49: ...device accepts NRZ data and a complimentary WCLK It also produces MFM data and clocks by sending the data through circuitry which decides when and where to write clocks on the data stream under the M...

Страница 50: ...the present bits to be written and producing three signals depending on what these bits are The three signals are EARLY LATE and NOMINAL They are used in conjunction with a delay line to cause the le...

Страница 51: ...ad or to store data on a write This time varies depending on the amount of processing the 8X300 must do to access the desired register After the data has been written or read the WDlOOO de asserts the...

Страница 52: ...rations and Data ReQuests DRQ to signal data ready to DMA controllers INTRQ and DRQ originate on the MFM generator U30 as an auxilIary function of the chip The WDlOOO sets INTRQ using INTCLK and sets...

Страница 53: ...fter the range has been verified adjust R22 to the final setting listed in the table Yl Frequency Identity Range Final Setting 20 000 MHz Ll 3 3 uh 9 0 11 0 MHz 10 0 MHz 1 KHz 17 360 MHz Ll 3 9 uh 7 5...

Страница 54: ...ntil the most stable display reading is obtained This indicates that the VCO is being locked on every attempt to read data 3 Turn off power to the board 4 Disconnect all test equipment 8 7 4 DRUN Adju...

Страница 55: ...4 Turn off power to the WDIOOO 5 Disconnect all test equipment 50...

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Страница 57: ...R and sets the interrupt status to Mode O During reset time the address and data bus go to a high impedance state and all control output signals go to the inactive state Note that RESET must be activ...

Страница 58: ...IS 16 6 10 10 II 15 15 10 14 19 23 23 18 21 16 L h 00 BC 01 DE 10 HL II SP 00 BC 01 DE 10 HL II IJ Load lfL Imo 01 _ _ dacrwmM d tbiI brte _ 1lCl UBC 0 UBC 0 2 Exchange Block Transfer Block Search Gro...

Страница 59: ...DE 10 IY II SP Rot Ie efIctrcu lor accumuililor Rotate left accumulotor Rototertqhtcireul4r occumulolor Rotateriqht ao umuililor RoI4leleilclfcul sr reql 001 C 010 D 011 I 100 H 101 L III A lnatrucllo...

Страница 60: ...sse HL X X X X I X I X blllnCTemeni abat decrement 16 blladd RLA RLCA RRA RRCA RL m RLC m RR m X I X X P 16 b ladd wilhcarry I bllsublract wllhcarry RotateaCCllmuletor Rotate and shih locaiLonl RRC m...

Страница 61: ...urn from interrupt instruction RET ED 4D sent by the CPU During two byte instruction fetches III is active as each opcode byte is fetched An jnterrupt ack nowledge is indicated when both III and ORO a...

Страница 62: ...Strobe Pulse From Peripheral Device input active Low The meaning 01 this signal dependo on the 01 operation selected lor Port A as lollows Oulpu Modo The iUve edge 01 this strobe _ by the per1pherol...

Страница 63: ...EO o I MOD I 1 0 O I 1 I MODE3 FIll B Mode CoD 1 W ffiDOJ o J D LID VECTOR VECTOR FIll 7 IDIettupt V W T J ID c 0 lETS liT TO OUTPUT 1 lETS liT TO INPUT Fill 8 YO lIogIotor Co IroI W fO Jii EF Jil E C...

Страница 64: ...ued the trigger mode for timer operation When OJ is reset to 0 the timer is triggered automatic ally The time constant word is programmed during an I O write operation which takes one machine cycle At...

Страница 65: ...either data or control Information as speCified by cm If 10RO and MI are active simultane oiisly the CPU is acknowledging an interrupt and the 510 automatically places itl Interrupt vector on the CPU...

Страница 66: ...hree bits Do D that point 10 the selected regiSter the second byte Is the actual control word that Is written Into the register to cor figure the SIO WRO is a special case in that all of the basic com...

Страница 67: ...ON SECTION TITLE 1 0 INTRODUCTION 2 0 TS 806C TAPE CONTROLLER BOARD DESCRIPTION 3 0 FUNCTION OF THE SYSTEM 4 0 OPERATION OF THE SYSTEM 5 0 INPUT OUTPUT PORT ASSIGNMENT AND TIMING 6 0 CONNECTOR DESCRIP...

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Страница 69: ...ation The TS 806e receives commands from the TS 806 to perform tape read write or erase functions all other data is passed through to the work station The system block diagram is shown in Figure 1 1 1...

Страница 70: ...en by a 4 MHz system or tape clock This clock is also used to generate the necessary timing for the memory control logic The Z80A CPU has a 16 bit address bus which can address up to 64 Kbytes for mem...

Страница 71: ...ins eight 64K x I jynamic memory devices only 60 Kbytes are accessible There are four kilobytes of EPROM 3 0 FUNCTION OF THE SYSTEM rhe TS 806C generates an 8 MHz clock and a 4 MHz clock These are sup...

Страница 72: ...the Z80A devices The high level of the clock must be between 4 4 V and 5 3 V and the low level must be between 0 3 V and 0 45 V see Figure 4 A transistor 2N2907 is used to pull the clock s output high...

Страница 73: ...memory The purpose of these resistors is to reduce the signal under shoot caused from the capacitance of the devices Tl T2 T3 T4 CLK 1 _ _ J 1 1 11 ___1 AO A15 _______x_________ MREQ __ __ 11 ________...

Страница 74: ...rols the tape drive operation 4 1 1 Output Latches from the computer The control signals to the tape drive are programmed by two data latches These latches are write only ports 4 1 1 1 Tape Output Lat...

Страница 75: ...X 1 RWD I FB 1 WEN 11 HSP 1 FWD REV 07 06 05 04 03 02 01 00 Reverse direction REV is 000 Active low causes the tape move in the reverse direction Forward direction FWD is 001 Active low causes the tap...

Страница 76: ...1 2 Input Latches to the controller The status of the tape controller is read through two input ports These ports are read only status line which are latched by the tape drive 4 1 2 1 Tape Status Inp...

Страница 77: ...ard or reverse command This signal goes true when the command is received and remain true until tape motion has stopped The time for slow speed commands is 30 milliseconds and for high speed commands...

Страница 78: ...e low on the SIO for the equivalent of a five byte transmission time before and after the data is transmitted During data transfer DTR is at a high level 5 0 Input Output Port Assignments and Timing 5...

Страница 79: ...LK J I 1 1 I IORQ WR MEMORY LATCH I I _ _ _ _ I Figure 7 Memory Latch Timing 5 3 SIlO Read Write Cycle Tl T2 TW T3 Tl T2 TW T3 CLK J J I I I I J I SID CS IORQ ____ I RD Ml HIGH DATA ________ _________...

Страница 80: ..._P2_ 5_ PI P4 __ _P3_ __________ Figure 9 Connector Positions Connector No PI P2 P5 P3 P4 Legend 13 Description POWER CONNECTOR RS422 CONNECTOR TS806 RS422 CONNECTOR TS800 TAPE INTERFACE CONNECTOR RES...

Страница 81: ...16 pin header on the PCB Rear panel 15 pin D type conn D conn Header Description 1 1 GND 9 2 TxD 2 3 TxD 10 4 RxD 3 5 RxD 11 6 RTS 4 7 RTS 12 8 CTS 5 9 CTS 13 10 TxC 6 11 TxC 14 12 RxC 7 13 RxC 15 14...

Страница 82: ...nnector 5 Pin Wafer Option PIN 1 2 3 4 5 7 0 SPECIFICATIONS Power Requirement Power Consumption DESCRIPTION C Opt n for lighted switch Void No pin Reset Signal Ground NC Not used 1 08 Amp 5 V TYPICAL...

Страница 83: ...Interrupt Priority 1st Priority SIO 2nd priority CTC 16...

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Страница 85: ...E LISTS This section contains the Repair Price List for Computers and the Systems Spare Parts Price List in effect at the printing date of this manual Use these lists for estimating repairs prices are...

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Страница 87: ...c Repair charge This additionalamount charged when an entire system is returned for repair Te eVideo will bill perabove price schedule when no trouble is found in the module returned for repair Outof...

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Страница 89: ...Systems Spare Parts Price List o TeleVideo Systems Inc...

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Страница 91: ...r s TS 802H Installation User s TS 803 Installation User s TS l602G Installation User s TS l602GH Installation User s TS 1603 Installation User s TS 806 Installation User s TS 806 20 Installation User...

Страница 92: ...e TS 803 1603 866 19 PCB Asy 5 n Winchester Disk Controller 806 806 20 866 19 PCB Asy 8 n Winchester Disk Controller 816 40 210 75 PCB Asy Floppy Disk Cont TS 802 Daughter Bd 656 87 PCB Asy Graphics T...

Страница 93: ...2100600 110 00 Case Top TS 802 1602G 2100700 85 00 Case Bottom TS 802 1602G 2100800 40 00 Bezel TS 802 1602G 2141700 70 20 Case Bottom TS 800A 2141800 97 80 Case Top TS 800A 2141900 20 00 Bezel TS 800...

Страница 94: ...40 IC I O Decode TS 1602G 55 80 IC Diagnostic EPROM TS a06 55 aO IC Diagnostic EPROM TS a06C 55 80 IC Diagnostic EPROM TS a16 55 80 IC Diagnostic EPROM TS 816 40 23 70 IC L2 7 System Program ROM WDC...

Страница 95: ...50 57 Pin TS 816 40H Internal for Winchester 2235600 42 36 Cbl Asy 25 20 Pin TS 816 40H Internal for Winchester 2008600 28 00 Harness Asy Power TS 802H 2007900 28 00 Harness Asy Power Cable 16 ft TS...

Страница 96: ...Crystal 15 MHz 2042800 27 00 Crystal 16 MHz MOT CTS HYT 2098604 4 50 Crystal 20 000 MHz 2035200 37 08 Crystal 23 814 MHz Kll14A MOT CTS 2099700 1 02 Insulator Mounting Pad For Crystal FANS 2099000 35...

Страница 97: ...S 1 50 Label Logo Plastic TeleVideo Systems 2 40 Label Logo Plastic TeleVideo Printer 72 Label Keyboard TS 800A 72 Label Keyboard TS 802 72 Label Keyboard TS 802H 72 Label Keyboard TS l602G 72 Label...

Страница 98: ...oltage Inductor 27uh Voltage Regulator LAS 16CB 2A 13 8Volts Resistor CF 390 Ohms 1 2Watt 5 IN759A Zener Diode Capacitor 220uf 16Volt Electrolytic Capacitor luf 600Volt Mylar 2SC2233 MJE13006 Diode 30...

Страница 99: ...806 Logic To Floppy WDC To Winchester 806 Logic To WOC 806 WOC To Winchester 806 Parallel Printer Spare Parts Mechanical TS802 800A cord for keyboard 3 amp 125V fuse 25 each keyswitch 10 position side...

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Страница 101: ...latest board assembly drawings and logic diagrams When ordering parts use the component type or value shown in the diagrams to refer to the TeleVideo part number listed in the Spare Parts Price List T...

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Страница 139: ...SELEcT BITS 4 1 DRUN D T RUN HFRQ HIGH I R1ii QUENCY r _ _ 1IOlU _ _ HO T SELECT NXlSS CONTROL J HSZ HS HUID SELECT BIT 2 tf I RESISTOR VALUES ARti IN OHMS lSI V4 w ri v IAt INSTRUCTION ODRESS UNES B...

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Страница 144: ......

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Страница 146: ......

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Страница 148: ......

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Страница 150: ......

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Страница 152: ......

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Страница 154: ......

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Страница 156: ......

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Страница 158: ......

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