Tektronix P6450, Инструкция по эксплуатации

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Reference
It is a good practice to take advantage of the unused clock and quali fi er channels
to increase your options for when you will latch data. Routing several clocks and
strobes in your design to the logic analyzer clock inputs will provide you with a
greater
fl exibility in the logic analyzer Setup menu.
As an example, look at a microprocessor with a master clock, data strobe, and an
address strobe. Routing all three of these signals to logic analyzer clock inputs
will enable you to latch data on the processor master clock, only when data is
strobed, or only when address is strobed. Some forethought in signal routing can
greatly expand the ways in which you can latch and analyze data.
A microprocessor also provides a good example of signals that can be useful
as quali
fi ers. There are often signals that indicate data reads versus data writes
(R/W), signals that show when alternate bus masters have control of the processor
buses (DMA), and signals that show when various memory devices are being
used (ChipSel). All of these signals are good candidates for assignment to
quali
fi er channels.
By logically ANDing the clock with one of these quali fi ers you can program the
logic analyzer to store only data reads or data writes. Using the DMA signal as a
quali
fi er provides a means of fi ltering out alternate bus master cycles. Chip selects
can limit data latching to speci fi c memory banks, I/O ports, or peripheral devices.
Demultiplexing Multiplexed Buses.
TLA5000B Series logic analyzers support 2X
demultiplexing. Each signal on a dual multiplexed bus can be demultiplexed into
its own logic analyzer channel. See the following table to determine the correct
channel groups to use.
Table 3: 2X Demultiplexing source-to-destination channel assignments
Destination channels receiving target system test data Source
connecting
channel
groups
TLA5204B TLA5203B TLA5202B TLA5201B
A3:7-0 D3:7-0 D3:7-0
C3:7-0 C3:7-0
A2:7-0 D2:7-0 D2:7-0
C2:7-0 C2:7-0
A1:7-0 D1:7-0 D1:7-0 D1:7-0
A0:7-0 D0:7-0 D0:7-0 D0:7-0
C3:7-0 C1:7-0 C1:7-0
C2:7-0 C0:7-0 C0:7-0
E3:7-0 E1:7-0
E2:7-0 E0:7-0
CLK:0 QUAL:1 QUAL:1
CLK:1 QUAL:0 QUAL:0
CLK:2 QUAL:3
CLK:3 QUAL:2
14 P6450 High-Density Logic Analyzer Probe Instruction Manual