Tektronix 318, Техническое руководство

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TM 11-6625-3145-14
Maintenance: Troubleshooting-318/338 Service
11. N & DELAY TEST
Program: N & DLY
Function:
Power on - The Event/Delay counter counts word "A" N times when functioning as the event counter, and counts a certain
number of clock signals for delay when functioning as the delay counter.
When functioning as the event counter, the MPU loads a small N value into the counter register and increments the
counter using clock pulses while observing the carrry bit. The Delay counter functions the same way, using the DELAY
value as the initial counter value. In both cases the number of clock signals needed to generate the carry are compared
with the expected values.
Troubleshooting - This is not a verification test, so no test result will appear on the CRT screen. This test should be
observed on an oscilloscope. The Troubleshooting routine automatically tests the N&DELAY counter by alternately
loading and running the counter, first with N values as the event counter, and then with DELAY values for the delay
counter. The user programs the N and DELAY values before beginning the test. This test will run continuously until the
user presses the STOP key. If no test values are entered, the N counter is set to 1 and the DELAY counter is set to
ZERO. In this case, the N&DELAY counter will not run. To run this test, N must be greater than 1, and DELAY must be
greater than 0.
Description: Refer to Figure 7-42. The Event Delay counter U158 (event/delay counter,
µ
PB3Z198R) on the A03 ACQ
Control board is controlled by three signals, CE , LOAD N, and LOAD DL from the SQRAM U144 (256 word X 4-bit RAM,
HM10422) on the A03 board. The counter generates N-1 as a carry when it reaches full count. This Event/Delay counter
has two registers, the one which holds the N value is called the N-register and the one which holds the DELAY value is
called the DL register.
In this test, the MPU writes 000F
hex
as the N value into the N-register at I/O addresses 41
hex
and 42
hex
, and 005A
hex
as the
DELAY value into the DL register at I/O address 43
hex
and 44
hex
.
Start flip-flop U124B (dual type D master-slave flip-flop, 10131) on the A03 board is set by START2 from U 110 (binary to
1-8 decoder/multiplexer, 10162) on the A03 board. U124B passes a clock signal generated by the MPU.
Latches U106 and U108 (hex D master-slave flip-flop, 10176) on the A03 board are set to hold data 1100b for the
SQRAM. They also enable U140 (hex AND-gate, 10197) and U154 (quad 2-input AND-gate, 10104) on the A03 board.
Those gates control the data supplied to the address line of the SQRAM.
The MPU writes the data already set in the latches into the SQRAM at address FF
hex
using the WRITE SQRAM signal
from U1 12 <6> (10162) on the A03 board. This data generates the LOAD N command for the Event/Delay counter. After
this setup, latches U106 and U108 (10176) are written to set the clock qualifier to off, which enables the MPU to send a
single clock. The MPU generates STEP CLK by writing at I/O address 55
hex
from U1 10 (10162) on the A03 board, using
FF
hex
as data. That is, the SQRAM delivers the data at address FF
hex
pointed to by the MPU Data to the Event/Delay
counter, it is LOAD N, and the strobe generator circuit on the A03 board generates TRIG CLK to the Event/Delay counter.
By this procedure, the N value of the N-register in the Event/Delay counter is loaded into the counter itself.
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