Tektronix 2213, Инструкция по эксплуатации

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Theory of Operation—2213 Service
such, must also be used to obtain the internal vertical mode
trigger signal.
When S305 is set to VERT MODE, the LO logic level on
the XY signal line is removed from both U305B pin 4 and
from U305D pins 12 and 13, pulling these inputs HI. In
either ADD or A L T VE R TIC A L MODE, U305C pin 9 and
U305B pin 5 are also pulled HI whenever a LO is not being
applied from S315.
The input conditions just described fo r U305B, U305D,
and U305C allow the logic levels on U315C pin 10 and
U315B pin 4 to control the states o f the CH 1 Trig and
CH 2 Trig trigger-selection signals. Input signals to pins 10
and 4 are obtained from the Channel Enable signals present
at pins 5 and 6 of Channel Switch U317A.
When CH 1 Enable is HI (selecting the Channel 1 signal
fo r display), U315C pin 10 is also HI and U315C pin 8 is
LO to disable the Channel 2 Trigger Pickoff Am plifier.
Concurrently U317A pin 6 applies a LO to U315B pin 4,
and the HI output obtained from U315B pin 6 as a result
enables the Channel 1 Trigger Pickoff Am plifier.
For A L T VER TICAL MODE displays, the output states
o f Channel Switch S317A are switched alternately, at the
end o f each sweep, in synchronization w ith the A lt Sync
signal. Therefore, on alternate sweeps, the logic levels on
U315C pin 10 and on U315B pin 4 also change states.
When the Channel 1 signal is being displayed, the
Channel 1 Trigger signal is selected as the internal source.
For Channel 2 signal displays, the Channel 2 Trigger signal
is selected.
An ADD VER TICAL MODE display causes both pin 5
and pin 6 o f U317A to be HI (see "Channel Switching
Logic" discussion fo r a description of the circuit operation).
The sum o f the two channel vertical signals is displayed,
and the sum of the two channel trigger signals is used as the
internal trigger signal.
Summation is accomplished by the HI logic levels from
IJ317A pins 5 and 6 causing both the CH 1 Trig and CH 2
Trig signals to go LO. With the input transistors to both
Trigger Pickoff Am plifiers biased o ff, additional circuitry
w ithin the Trigger Pickoff amplifiers biases on the pickoff
transistors fo r both Channel 1 and Channel 2 (see the
Channel 1 and Channel 2 Preamplifier circuit descriptions.
A CHOP V E R TIC A L MODE display also uses the sum of
the two internal trigger signals, but the switching logic
involved is different from the ADD VER TIC AL MODE
display. With S315 set to CHOP, a LO logic level is applied
to U305B pin 5 and to U305C pin 9 from the XY signal
line via contacts on S315, S317, and S305. The outputs of
both U305C and U305B are LO and are applied to the
wired-AND connection on the CH 1 Trig and C H 2 T rig
signal lines. These LO signals override the outputs from
U315C and U315B to hold the input transistors o f both
Channel 1 and Channel 2 Trigger Pickoff Am plifiers biased
off. Channel 1 and Channel 2 Trigger signals are summed
as described previously fo r the ADD VE R TIC A L MODE
display.
X-Y MODE. When the SEC/DIV switch is set to X-Y,
the Channel 2 signal is selected as the input to the Vertical
Output A m plifier to provide the X-Axis deflection. The
Channel 1 Trigger signal provides the X-Axis signal to the
X Y A m plifier (Diagram 7) via the Internal Trigger
Am plifier. Therefore, the Trigger Switching Logic circuit
must have inputs that enable the Channel 1 Trigger Pickoff
Am plifier.
The LO logic level signal supplied by the XY signal line
to S305 and S317 is removed by switching contacts on the
SEC/DIV switch. Concurrently, a LO logic level is placed
on the X Y signal line by contacts on the SEC/DIV switch.
The LO on the XY line is applied to the Reset input o f
U317A to select the Channel 2 signal fo r display. This LO
is also applied to U305B pin 4 and to U305D pin 13 via
U305A to set up the Trigger Switching Logic that enables
the Channel 1 Trigger Pickoff Am plifier.
A LO on U305B pin 4 ensures that the output of U305B
pin 6 is a LO, which is applied to the CH 1 Trig signal line
to disable the Channel 2 Trigger Pickoff Am plifier. The LO
on U305D pin 13 is gated to U315B pin 5. With U315B
pin 5 LO, the output o f U315B w ill be a HI that, when
ANDed with the HI present from U305C pin 8, enables the
Channel 1 Trigger Pickoff Am plifier.
TRIGGER
The Trigger circuit, shown on Diagram 4, is composed of
the Internal and External Trigger Amplifiers, Source­
switching circuit, and Trigger Generator circuit. Included
in the Trigger Generator circuit is the Auto Trigger and
Auto Baseline circuitry and the TV Triggering circuitry.
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