1000BASE-T1 SFP MODULE
User Manual
17
3.3.4
I2C access to the 88Q2112_A2 transceiver
The 88Q2112_A2 PHY listens as slave on the 7-bit address 0x40. Every internal register
of the PHY (16 bits) is accessed by defining the Device Number (1 byte) and the
Register address (2 bytes). The I2C Memory address is mapped as:
Address
Register name
0x00
Device number
0x01
Register_address_MSB
0x02
Register_address_LSB
0x03
PHY_Register_Operation_Status
0x04
PHY_Register_data_MSB
0x05
PHY_Register_data_LSB
Table 3-2: Register addresses
3.3.4.1
Register description
Device number:
Defines the device number of the register to access
Register_address_MSB:
Defines the Most significant byte of the register to access
Register_address_LSB:
Defines the Less Significant Byte of the register to access
PHY_Register_Operation_Status
o
Bit 0
–
Read Start Condition Flag (Read/Write)
This flag is set by the master after specifying the first 3 bytes of the register
(Devices number, Register_address_MSB and Register_address_LSB) when a
read operation is trigged.
o
Bit 1
–
Read In Progress Flag (Read)
This flag is set by the slave during the reading operation
o
Bit 2
–
Read Operation Done Flag (Read)
This flag is set by the slave when the reading operation is finished. This flag can
be read after triggering the read to ensure that the data has finished reading.
