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FLEX-IMX8M-Mini HARDWARE MANUAL

– VER 1.00 – JAN 31 2020

Page

5.14. Input Power Requirements

The FLEX-IMX8M-Mini is designed to be driven with a single input power rail.
The power domain pins have to be connected as follow:

•

All GND pins have to be connected to the carrier board ground pane.

•

All VSYS pins should be connected to the main power source.

Table 28 - Input Power Signals

POWER

Rail

Nominal Input

Input Range

Maximum Input Ripple

VSYS

+4.75V to +5.25V

+/- 50mV

5.14.1. Reference and Output Power

The FLEX-IMX8M-Mini is a versatile system on module that can be incorporated in an embedded
system where the carrier board will have additional requirements for 3.3V.

For this purpose the FLEX-IMX8M-Mini integrates a 3.3V reference voltage pin and an additional 3.3V
power output.

Table 29 - Power Management Signals

PIN

Description

3.3V Reference Voltage for I/O

3.3V Output Voltage maximum 500mA

Содержание FLEX-IMX8M-Mini

Страница 1: ...FLEX IMX8M Mini SYSTEM ON MODULE PRODUCT MANUAL WITH NXP i MX8M Mini SoC VER 1 00 January 31 2020...

Страница 2: ...MX8M Mini HARDWARE MANUAL VER 1 00 JAN 31 2020 Page 2 of 48 REVISION HISTORY Revision Date Originator Notes 0 1 November 6 2019 TechNexion Preliminary 1 00 January 31 2020 TechNexion General Public Re...

Страница 3: ...Assignment 18 5 FLEX IMX8M Mini External Interfaces 27 5 1 Ethernet 27 5 2 MIPI Display 28 5 3 MIPI Camera 30 5 4 Audio Interface 32 5 5 PCI Express 34 5 6 Universal Serial Bus USB Interface 35 5 7 SD...

Страница 4: ...nal Description 35 Table 17 USB OTG Signal Description 36 Table 18 SDIO Signal Description 37 Table 19 UART3 Signal Description 39 Table 20 UART2 Signal Description 39 Table 21 SPI Signal Description...

Страница 5: ...ar approach offered by the FLEX Compute Module gives your project scalability fast time to market and upgradability while reducing engineering risk and maintain a competitive total cost of ownership 2...

Страница 6: ...Page 6 of 48 2 2 Block Diagram Figure 2 FLEX IMX8 Mini System on Module Block Diagram Overview 2 3 Dimensional Drawing The FLEX IMX8 Mini System on Module is an ultra compact module in FLEX form facto...

Страница 7: ...e 7 of 48 2 4 Component Location Figure 4 FLEX IMX8M Mini Top View Figure 5 FLEX IMX8M Mini Bottom View No Description No Description 1 NXP i MX8M Mini Processor 4 Wi Fi Bluetooth Module optional 2 Me...

Страница 8: ...ore platforms up to 1 8GHz per core o 32KB L1 I Cache 32 kB L1 D Cache o 512 kB L2 Cache o 1x Arm Cortex M4 core up to 400MHz o 16 kB L1 I Cache 16 kB L2 D Cache GPU o 3D GPU 1x shader OpenGL ES 2 0 o...

Страница 9: ...FLEX IMX8M Mini HARDWARE MANUAL VER 1 00 JAN 31 2020 Page 9 of 48 Figure 6 NXP i MX8M Mini Processor Blocks...

Страница 10: ...I PMIC Power standby request input from processor K24 NAND_DAT A01 GPIO3_IO07 IRQ_B O PMIC Interrupt Signal F24 RTC_RESET _B RTC_RESET_ B RTC_RESET _B O PMIC RTC Reset Signal A26 RTC_XTALI RTC_XTALI...

Страница 11: ...turers have been validated and tested on the FLEX IMX8M Mini System on Module Kingston eMMC Micron eMMC Sandisk iNAND Table 4 eMMC Signal Description CPU BALL CPU PAD NAME Signal V I O Description M26...

Страница 12: ...9377 are IEEE 802 11 ac a b g n 2 4 5Ghz Bluetooth 5 MHF4 antenna connector Linux and Android drivers Wi Fi BT module board certifications with multiple antennas o FCC USA o IC Canada o ETSI Europe o...

Страница 13: ...IO3_IO00 WL_HOST_WAKE O Host wake up Signal from the module to the host indicating that the module requires Attention Asserted Host device must wake up or remain awake Deserted Host device may sleep w...

Страница 14: ...Interchip Sound I2S channel transmit data line AC18 SAI1_TXC SAI1_TXC O Integrated Interchip Sound I2S channel word clock signal AB19 SAI1_TXFS SAI1_TXFS O Integrated Interchip Sound I2S channel frame...

Страница 15: ...port internal delay and external delay on Rx path Supports Atheros Green ETHOS power saving modes with internal automatic DSP power saving scheme Supports IEEE 802 3az Energy Efficient Ethernet n Supp...

Страница 16: ...RGMII transmit data 3 AF24 ENET_TX_CTL ETH_TXEN 32 RGMII transmit enable AE26 ENET_RXC ETH_RXCLK 31 RGMII receive clock AE27 ENET_RD0 ETH_RXD0 29 RGMII receive data 0 AD27 ENET_RD1 ETH_RXD1 28 RGMII...

Страница 17: ...trol and status such as putting selected cores into reset and or debug mode and the ability to monitor individual core status signals via JTAG JTAG port interfaces the M4 and Cortex A53 Cores DAP debu...

Страница 18: ...nput power 4 75 to 5 25V 6 VSYS 5V0 P System input power 4 75 to 5 25V 7 3V3_REF 3V3 P 3 3V Reference Voltage for I O 8 3V3_VDD 3V3 P 3 3V Output Voltage 9 SYS_nRST 1V8 I Power Reset pin connected to...

Страница 19: ...ED1_nLink100 2V5 O Gigabit Ethernet 100Mbit sec LED link indicator 25 AR8035 pin 21 LED1_ACT 2V5 O Gigabit Ethernet LED Activity indicator 26 AR8035 pin 22 LED1_nLink1000 2V5 O Gigabit Ethernet 1000Mb...

Страница 20: ...O MIPI Display Serial Interface clock pair negative signal 56 NC Not Connected 57 B11 MIPI_DSI_CLK_ P MIPI_DSI_CLK_P 1V8 O MIPI Display Serial Interface clock pair positive signal 58 GND P Ground 59 G...

Страница 21: ...al 85 NC Not Connected 86 GND P Ground 87 GND P Ground 88 A17 MIPI_CSI_D2_N MIPI_CSI_D2_N 1V8 I MIPI Camera Serial Interface data pair 2 negative signal 89 NC Not Connected 90 B17 MIPI_CSI_D2_P MIPI_C...

Страница 22: ...ss Wake Signal 120 NC Not Connected 121 AB22 SAI2_RXC GPIO4_IO22 3V3 I PCI Express Clock Request Signal 122 NC Not Connected 123 NC Not Connected 124 GND P Ground 125 NC Not Connected 126 NC Not Conne...

Страница 23: ...ND P Ground 165 NC Not Connected 166 K23 NAND_DATA02 GPIO3_IO08 3V3 I O General Purpose Input Output for USB Over Current Detection 167 GND P Ground 168 F22 USB1_VBUS USB1_VBUS 5V I O Universal Serial...

Страница 24: ...SAI3_RXD SAI3_RXD 3V3 I Integrated Interchip Sound I2S channel receive data line 201 E10 I2C3_SCL I2C3_SCL 3V3 O I2C bus clock line 202 AC6 SAI3_TXFS SAI3_TXFS 3V3 O Integrated Interchip Sound I2S ch...

Страница 25: ...ted 223 W23 SD2_CLK USDHC2_CLK 1V8 3V3 O MMC SDIO Clock 224 NC Not Connected 225 W24 SD2_CMD USDHC2_CMD 1V8 3V3 I O MMC SDIO Command 226 NC Not Connected 227 AB23 SD2_DATA0 USDHC2_DATA0 1V8 3V3 IO MMC...

Страница 26: ...mit clear to send signal 246 N23 NAND_DATA03 GPIO3_IO09 3V3 I O General Purpose Input Output 247 GND P Ground 248 AC13 SAI5_RXD3 GPIO3_IO24 3V3 I O General Purpose Input Output 249 BOOT SELECT PIN 250...

Страница 27: ...ential pair 0 positive signal 13 AR8035 pin 15 GBE_MDI2 2V5 I O Gigabit Ethernet Media Dependent Interface MDI differential pair 2 positive signal 14 AR8035 pin 10 GBE_MDI0 2V5 I O Gigabit Ethernet Me...

Страница 28: ...ort 1 to 4 Data Lanes Optional bidirectional support on lane 0 Supports High Speed and Low Power operation Support for all DSI data types and formats Virtual Channel support Supports ULPS mode Full Lo...

Страница 29: ...I Display Serial Interface data pair 2 positive signal 49 A13 MIPI_DSI_D3_N MIPI_DSI_D3_N 1V8 O MIPI Display Serial Interface data pair 3 negative signal 51 B13 MIPI_DSI_D3_P MIPI_DSI_D3_P 1V8 O MIPI...

Страница 30: ...bps 1 5Gbps per lane providing 4K 30fps capability for the 4 lanes Supports 10Mbps data rate in low power mode Includes high speed deserializers Loopback testability support Support for all CSI 2 data...

Страница 31: ...Serial Interface data pair 1 negative signal 84 B15 MIPI_CSI_D1_P MIPI_CSI_D1_P 1V8 I MIPI Camera Serial Interface data pair 1 positive signal 88 A17 MIPI_CSI_D2_N MIPI_CSI_D2_N 1V8 I MIPI Camera Ser...

Страница 32: ...clock and frame sync supporting 1 data line Each data line can support a maximum Frame size of 32 words Word size of between 8 bits and 32 bits Word size configured separately for first word and rema...

Страница 33: ...Sound I2S channel word clock signal 208 AD6 SAI3_MCLK SAI3_MCLK 3V3 O Integrated Interchip Sound I2S channel master clock signal Table 14 I2S 2 Audio Signal Description PIN CPU BALL CPU PAD NAME Sign...

Страница 34: ...PHY 1 5 2 5 3 0 5 0 6 0 Gbps Serializer Deserializer Compliant with PCI Express Base Specification 2 1 Compliant with PIPE Specification 2 0 8 16 20 40 bit CMOS Interface for Transmitter and Receiver...

Страница 35: ...ol and host negotiation protocol Support charger detection USB 2 0 Host Controller High Speed Full Speed Low Speed Host Only core HS FS LS UTMI compliant interface For additional details please refer...

Страница 36: ...tial pair negative signal 162 B22 USB1_DP USB1_DP 3V3 I O Universal Serial Bus differential pair positive signal 166 K23 NAND_DATA02 GPIO3_IO08 3V3 I O General Purpose Input Output for USB Over Curren...

Страница 37: ...Supports 1 bit 4 bit SD and SDIO modes 1 bit 4 bit 8 bit MMC modes The MMC SD SDIO host controller can support a single MMC SD SDIO card or device For additional details please refer to the Ultra Secu...

Страница 38: ...baud rates up to 4 Mbps 32 byte FIFO on Tx and 32 half word FIFO on Rx supporting auto baud Serial IR interface low speed IrDA compatible up to 115 2 Kbit s Hardware flow control support for a reques...

Страница 39: ...SPI1_MISO UART3_CTS_B 3V3 O Universal Asynchronous Receive Transmit clear to send signal Table 20 UART2 Signal Description PIN CPU BALL CPU PAD NAME Signal V I O Description 239 E15 UART2_TXD UART2_TX...

Страница 40: ...ransmit and receive data Polarity and phase of the Chip Select SS and SPI Clock SCLK are configurable Direct Memory Access DMA support For additional details please refer to the Enhanced Configurable...

Страница 41: ...ional details please refer to the I2C Controller I2C chapter of the i MX8M Mini Applications Processor Reference Manual Table 22 I2 C Bus Signal Description PIN CPU BALL CPU PAD NAME Signal V I O Desc...

Страница 42: ...anual Table 23 GPIO Signal Description PIN CPU BALL CPU PAD NAME Signal V I O Description 240 AC15 SAI5_RXC GPIO3_IO20 3V3 I O General Purpose Input Output 242 P23 NAND_DATA00 GPIO3_IO06 3V3 I O Gener...

Страница 43: ...rammed to be active in low power mode Can be programmed to be active in debug mode Interrupts at compare and rollover For additional details please refer to the Pulse Width Modulation PWM chapter of t...

Страница 44: ...25 eMMC Boot Mode Configuration PIN Description 249 HIGH 3V3 251 HIGH 3V3 253 HIGH 3V3 255 HIGH 3V3 5 13 2 Serial Downloader Boot Mode To boot the FLEX IMX8M Mini in Serial Download Mode The boot sig...

Страница 45: ...ce Table 28 Input Power Signals POWER Rail Nominal Input Input Range Maximum Input Ripple VSYS 5V 4 75V to 5 25V 50mV 5 14 1 Reference and Output Power The FLEX IMX8M Mini is a versatile system on mod...

Страница 46: ...The FLEX IMX8M Mini can be ordered in custom tailored configuration to meet special application requirements and conditions according to the following custom part number creation rules Custom part nu...

Страница 47: ...nts or other intellectual property of the third party or a license from TechNexion under the patents or other intellectual property of TechNexion TechNexion products are not authorized for use in safe...

Страница 48: ...this publication To the extent permitted by law no liability including liability to any person by reason of negligence will be accepted by TechNexion Ltd its subsidiaries or employees for any direct o...

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