FLEX-IMX8M-Mini HARDWARE MANUAL
– VER 1.00 – JAN 31 2020
Page
34
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5.5. PCI Express
This block provides information regarding PCIe PHY and its features. PCIe PHY supports 6.0 Gbps
data rate and complies to PCI Express base specification 2.1. The functions that are performed by the
transceiver include serializing the 8B/10B encoded data for transmission, de-serializing received code
groups, and word alignment.
When transmitting, the transceiver accepts two or four 10-bit 8B/10B encoded transmit characters,
latches them and serializes the data onto the PCIE_TX_P/PCIE_TX_N differential outputs at 1.5 / 2.5
/ 3.0 / 5.0 / 6.0 Gbps. It also performs 8B/10B encoding for 8-bit data from the PIPE interface.
When receiving, the transceiver also samples received serial data on the PCIE_RX_P / PCIE_RX_N
differential inputs, deserializes it into two or four 10-bit received characters and detects the K28.5
character (0011111010 or 1100000101) for word alignment. It also applies 8B/10B decoding for 8-bit
data to the PIPE interface. PCIe PHY core contains on-chip PLL circuitry for synthesis of the baud-
rate transmitting clocks, and extraction of the retimed clocks from the received serial stream.
The following list the key features of the PCIe PHY:
•
1.5 / 2.5 / 3.0 / 5.0 / 6.0 Gbps Serializer / Deserializer
•
Compliant with PCI Express Base Specification 2.1
•
Compliant with PIPE Specification 2.0
•
8 / 16 / 20 / 40-bit CMOS Interface for Transmitter and Receiver
•
25 / 100 MHz Reference Clock
•
K28.5 Detection for Word Alignment
•
8B/10B Encoding / Decoding
•
Receiver Detection
•
Supports Spread Spectrum Clocking in Transmitter and Receiver
For a
dditional details, please refer to the “PCI Express (PCIe)” chapter of the “i.MX8M Mini
Applications Processor
Reference Manual”.
Table 15 - PCI Express Signal Description
PIN
CPU
BALL
CPU PAD NAME
Signal
V
I/O
Description
117
AG7
SAI3_RXC
GPIO4_IO29
3V3
I
PCI Express reset signal
119
AC19
SAI2_RXFS
GPIO4_IO21
3V3
I
PCI Express Wake Signal
121
AB22
SAI2_RXC
GPIO4_IO22
3V3
I
PCI Express Clock Request
Signal
129
A21
PCIE_CLK_N
PCIE_CLK_N
1V8
O
PCI Express clock differential pair
negative signal
131
B21
PCIE_CLK_P
PCIE_CLK_P
1V8
O
PCI Express clock differential pair
positive signal
135
A20
PCIE_TXN_N
PCIE_TXN_N
1V8
O
PCI Express Receive input
differential pair negative signal
137
B20
PCIE_TXN_P
PCIE_TXN_P
1V8
O
PCI Express Receive input
differential pair positive signal
141
A19
PCIE_RXN_N
PCIE_RXN_N
1V8
I
PCI Express Receive input
differential pair negative signal
143
B19
PCIE_RXN_P
PCIE_RXN_P
1V8
I
PCI Express Receive input
differential pair positive signal
NOTE: The PCIE_TX pair has decoupling capacitors on the FLEX Compute Module valued 10nF
