−
12
−
Pin No.
Symbol
I/O
Functional Description
Remarks
1
TEST0
I
Tes t mode terminal. Normally, keep at open.
With pull-up resistor.
2
HSO
O
3
UHSO
O
Playback speed mode flag output terminal.
UHSO
HSO
Playback Speed
H H Normal
H L 2
times
L H 4 times
L L
4 EMPH
O
Subcode Q data emphasis flag output terminal.
Emphasis ON at “H” level and OFF at “L” level.
The output polarity can invert by command.
5 LRCK
O
Channel clock output terminal. (44.1 kHz)
L-ch at “L” level and R-ch at “H” level. The output polarity can
invert by command.
6 V
SS
Digital GND terminal.
7
BCK
O
Bit clock output terminal. (1.4112 MHz)
8
AOUT
O
Audio data output terminal.
9 DOUT
O
Digital
data
output
terminal.
10 MBOV
O
Buffer memory over signal output terminal.
Over at “H” level.
11 IPF O
Correction flag output terminal.
At “H” level, AOUT output is made to correction impossibility
by C
2
correction processing.
12 SBOK
O
Subcode Q data CRCC check adjusting result output
terminal. The adjusting result is OK at “H” level.
13 CLCK
I/O
Subcode P~W data readout clock input/output terminal.
This terminal can select by command bit.
Schmitt input
14 V
DD
Digital power supply voltage terminal.
15 V
SS
Digital GND terminal.
16
DATA
O
Subcode P~W data output terminal.
17
SFSY
O
Play-back frame sync signal output terminal.
18 SBSY
O
Subcode
block
sync
signal
output
terminal.
19
SPCK
O
Processor status signal readout clock output terminal.
20
SPDA
O
Processor status signal output terminal.
21 COFS
O
Correction frame clock output terminal.
(7.35 kHz)
22 MONIT
O
Internal signal (DSP internal flag and PLL clock) output
terminal. Selected by command.
This terminal output the text data with serial by command.
23 V
DD
Digital power supply voltage terminal.
24 TESIO0 I
Tes t input/output terminal. Normally, keep at “L” level.
The terminal that inputted the clock for read of text data by
command.
25 P2V
REF
PLL double reference voltage supply terminal.
26
HSSW
O
This terminal is used to output PV
REF
or HiZ by command.
2-state output.
(PV
REF
, HiZ)
27
ZDET
O
1 bit DA converter zero detect flag output terminal.
28 PDO
O
Phase difference signal output terminal of EFM signal and
PLCK signal.
3-state output.
(P2V
REF
, PV
REF
, V
SS
)
Содержание CR-L600
Страница 3: ...2 ADJUSTMENTS AND CHECKS 3 調整と確認 準 備 中 Preliminary ...
Страница 4: ... 4 準 備 中 Preliminary ...
Страница 5: ... 5 準 備 中 Preliminary ...
Страница 18: ... 18 4 EXPLODED VIEWS AND PARTS LIST 分解図とパーツリスト EXPLODED VIEW 1 ...
Страница 20: ...EXPLODED VIEW 2 20 ...
Страница 22: ...5 PC BOARDS AND PARTS LIST 22 基板図とパーツリスト MAIN PCB ...
Страница 23: ... 23 INPUT PCB CD PCB ...
Страница 24: ... 24 FRONT PCB AMP PCB PHONE JACK PCB ...
Страница 28: ...8 6 7 4 5 2 3 1 E D C B A CD Receiver C CR R L L6 60 00 0 1 st Issue November 2002 BLOCK DIAGRAM CR L600 ...
Страница 29: ...8 6 7 4 5 2 3 1 E D C B A CD Receiver C CR R L L6 60 00 0 1 st Issue November 2002 WIRING DIAGRAM CR L600 ...