119
ARC CPU Address Decoder Registers
DesignWare ARC AXC003 CPU Card User Guide
Version 6323-018
Synopsys, Inc.
May 2017
23:20
SLV_OFFSET5
RW
0*
Address offset for address aperture[5]
1)
27:24
SLV_OFFSET6
RW
0*
Address offset for address aperture[6]
1)
31:28
SLV_OFFSET7
RW
0*
Address offset for address aperture[7]
1)
1) Same encoding as SLV_OFFSET0
CPU_A_OFFSET1: ARC CPU Address Offset Register 1
Address offset:
0x102C
Reset value:
0x0ED0_3210
Table 9
CPU_A_OFFSET1 Register
Legend: * reset value
Bit
Name
Access Value Description
3:0
SLV_OFFSET8
RW
Address offset for address aperture[8]
0*
0*256MB
1
1*256MB
…
….
15
15*256MB
7:4
SLV_OFFSET9
RW
1*
Address offset for address aperture[9]
1)
11:8
SLV_OFFSET10
RW
2*
Address offset for address aperture[10]
1)
15:12
SLV_OFFSET11
RW
3*
Address offset for address aperture[11]
1)
19:16
SLV_OFFSET12
RW
0*
Address offset for address aperture[12]
1)
23:20
SLV_OFFSET13
RW
D*
Address offset for address aperture[13]
1)
27:24
SLV_OFFSET14
RW
E*
Address offset for address aperture[14]
1)
31:28
SLV_OFFSET15
RW
0*
Address offset for address aperture[15]
1)
1) Same encoding as SLV_OFFSET8
CPU_A_UPDATE: ARC CPU Update Register
Address offset:
0x1034
Reset value:
0x0000_0000
Table 10 CPU_A_UPDATE Register
Legend: * reset value
Bit
Name
Access Value Description
0
UPDATE
RW1C
0*
All the address aperture configuration registers (i.e. *_A_SLV and
*_A_BOOT) are double-buffered. The newly programmed values
will be only be forwarded to
the address decoder after writing a ‘1’
to this bit.
31:1
Reserved
R
0x0*